Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:09:59.609813 lava-dispatcher, installed at version: 2024.01
2 14:09:59.610658 start: 0 validate
3 14:09:59.611142 Start time: 2024-11-10 14:09:59.611110+00:00 (UTC)
4 14:09:59.611700 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:09:59.612287 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:09:59.657661 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:09:59.658216 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:09:59.691530 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:09:59.692423 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 14:09:59.724596 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:09:59.725066 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:09:59.759253 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 14:09:59.760053 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 14:09:59.805167 validate duration: 0.19
16 14:09:59.806637 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:09:59.807266 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:09:59.807851 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:09:59.808622 Not decompressing ramdisk as can be used compressed.
20 14:09:59.809128 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 14:09:59.809417 saving as /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/ramdisk/initrd.cpio.gz
22 14:09:59.809698 total size: 5628140 (5 MB)
23 14:09:59.851456 progress 0 % (0 MB)
24 14:09:59.861076 progress 5 % (0 MB)
25 14:09:59.866510 progress 10 % (0 MB)
26 14:09:59.870125 progress 15 % (0 MB)
27 14:09:59.874136 progress 20 % (1 MB)
28 14:09:59.877739 progress 25 % (1 MB)
29 14:09:59.881712 progress 30 % (1 MB)
30 14:09:59.885683 progress 35 % (1 MB)
31 14:09:59.889320 progress 40 % (2 MB)
32 14:09:59.893296 progress 45 % (2 MB)
33 14:09:59.896814 progress 50 % (2 MB)
34 14:09:59.900771 progress 55 % (2 MB)
35 14:09:59.904710 progress 60 % (3 MB)
36 14:09:59.908266 progress 65 % (3 MB)
37 14:09:59.912190 progress 70 % (3 MB)
38 14:09:59.915731 progress 75 % (4 MB)
39 14:09:59.919485 progress 80 % (4 MB)
40 14:09:59.922830 progress 85 % (4 MB)
41 14:09:59.926571 progress 90 % (4 MB)
42 14:09:59.930206 progress 95 % (5 MB)
43 14:09:59.933534 progress 100 % (5 MB)
44 14:09:59.934206 5 MB downloaded in 0.12 s (43.12 MB/s)
45 14:09:59.934782 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:09:59.935715 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:09:59.936053 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:09:59.936356 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:09:59.936846 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/kernel/Image
51 14:09:59.937108 saving as /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/kernel/Image
52 14:09:59.937329 total size: 45713920 (43 MB)
53 14:09:59.937548 No compression specified
54 14:09:59.969893 progress 0 % (0 MB)
55 14:09:59.997950 progress 5 % (2 MB)
56 14:10:00.026230 progress 10 % (4 MB)
57 14:10:00.054994 progress 15 % (6 MB)
58 14:10:00.082799 progress 20 % (8 MB)
59 14:10:00.110226 progress 25 % (10 MB)
60 14:10:00.137979 progress 30 % (13 MB)
61 14:10:00.166128 progress 35 % (15 MB)
62 14:10:00.193773 progress 40 % (17 MB)
63 14:10:00.221163 progress 45 % (19 MB)
64 14:10:00.249090 progress 50 % (21 MB)
65 14:10:00.277258 progress 55 % (24 MB)
66 14:10:00.305064 progress 60 % (26 MB)
67 14:10:00.332221 progress 65 % (28 MB)
68 14:10:00.360353 progress 70 % (30 MB)
69 14:10:00.388152 progress 75 % (32 MB)
70 14:10:00.415969 progress 80 % (34 MB)
71 14:10:00.443644 progress 85 % (37 MB)
72 14:10:00.471819 progress 90 % (39 MB)
73 14:10:00.500107 progress 95 % (41 MB)
74 14:10:00.528885 progress 100 % (43 MB)
75 14:10:00.529465 43 MB downloaded in 0.59 s (73.63 MB/s)
76 14:10:00.529994 end: 1.2.1 http-download (duration 00:00:01) [common]
78 14:10:00.530915 end: 1.2 download-retry (duration 00:00:01) [common]
79 14:10:00.531235 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:10:00.531544 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:10:00.532078 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 14:10:00.532389 saving as /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 14:10:00.532620 total size: 53209 (0 MB)
84 14:10:00.532853 No compression specified
85 14:10:00.577553 progress 61 % (0 MB)
86 14:10:00.578409 progress 100 % (0 MB)
87 14:10:00.578945 0 MB downloaded in 0.05 s (1.10 MB/s)
88 14:10:00.579428 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:10:00.580300 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:10:00.580566 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:10:00.580829 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:10:00.581282 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 14:10:00.581521 saving as /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/nfsrootfs/full.rootfs.tar
95 14:10:00.581724 total size: 474398908 (452 MB)
96 14:10:00.581933 Using unxz to decompress xz
97 14:10:00.622567 progress 0 % (0 MB)
98 14:10:01.710006 progress 5 % (22 MB)
99 14:10:03.159105 progress 10 % (45 MB)
100 14:10:03.600494 progress 15 % (67 MB)
101 14:10:04.359165 progress 20 % (90 MB)
102 14:10:04.869740 progress 25 % (113 MB)
103 14:10:05.219110 progress 30 % (135 MB)
104 14:10:05.819935 progress 35 % (158 MB)
105 14:10:06.677239 progress 40 % (181 MB)
106 14:10:07.451103 progress 45 % (203 MB)
107 14:10:08.056041 progress 50 % (226 MB)
108 14:10:08.678203 progress 55 % (248 MB)
109 14:10:09.883784 progress 60 % (271 MB)
110 14:10:11.339053 progress 65 % (294 MB)
111 14:10:12.999116 progress 70 % (316 MB)
112 14:10:16.140137 progress 75 % (339 MB)
113 14:10:18.600782 progress 80 % (361 MB)
114 14:10:21.553373 progress 85 % (384 MB)
115 14:10:24.692325 progress 90 % (407 MB)
116 14:10:27.881700 progress 95 % (429 MB)
117 14:10:31.054125 progress 100 % (452 MB)
118 14:10:31.067895 452 MB downloaded in 30.49 s (14.84 MB/s)
119 14:10:31.068910 end: 1.4.1 http-download (duration 00:00:30) [common]
121 14:10:31.070681 end: 1.4 download-retry (duration 00:00:30) [common]
122 14:10:31.071246 start: 1.5 download-retry (timeout 00:09:29) [common]
123 14:10:31.071806 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 14:10:31.072708 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/modules.tar.xz
125 14:10:31.073201 saving as /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/modules/modules.tar
126 14:10:31.073643 total size: 11611892 (11 MB)
127 14:10:31.074098 Using unxz to decompress xz
128 14:10:31.113701 progress 0 % (0 MB)
129 14:10:31.181573 progress 5 % (0 MB)
130 14:10:31.257413 progress 10 % (1 MB)
131 14:10:31.355799 progress 15 % (1 MB)
132 14:10:31.449069 progress 20 % (2 MB)
133 14:10:31.528991 progress 25 % (2 MB)
134 14:10:31.605934 progress 30 % (3 MB)
135 14:10:31.684917 progress 35 % (3 MB)
136 14:10:31.757606 progress 40 % (4 MB)
137 14:10:31.834345 progress 45 % (5 MB)
138 14:10:31.918816 progress 50 % (5 MB)
139 14:10:31.996212 progress 55 % (6 MB)
140 14:10:32.080873 progress 60 % (6 MB)
141 14:10:32.161066 progress 65 % (7 MB)
142 14:10:32.240810 progress 70 % (7 MB)
143 14:10:32.317936 progress 75 % (8 MB)
144 14:10:32.401887 progress 80 % (8 MB)
145 14:10:32.482465 progress 85 % (9 MB)
146 14:10:32.561726 progress 90 % (9 MB)
147 14:10:32.639929 progress 95 % (10 MB)
148 14:10:32.716896 progress 100 % (11 MB)
149 14:10:32.729429 11 MB downloaded in 1.66 s (6.69 MB/s)
150 14:10:32.730291 end: 1.5.1 http-download (duration 00:00:02) [common]
152 14:10:32.731876 end: 1.5 download-retry (duration 00:00:02) [common]
153 14:10:32.732443 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 14:10:32.732956 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 14:10:48.672152 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/970720/extract-nfsrootfs-t_9a5b3f
156 14:10:48.672742 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 14:10:48.673027 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 14:10:48.673736 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd
159 14:10:48.674257 makedir: /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin
160 14:10:48.674603 makedir: /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/tests
161 14:10:48.674921 makedir: /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/results
162 14:10:48.675248 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-add-keys
163 14:10:48.675764 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-add-sources
164 14:10:48.676348 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-background-process-start
165 14:10:48.676961 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-background-process-stop
166 14:10:48.677517 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-common-functions
167 14:10:48.678023 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-echo-ipv4
168 14:10:48.678523 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-install-packages
169 14:10:48.679043 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-installed-packages
170 14:10:48.679529 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-os-build
171 14:10:48.680059 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-probe-channel
172 14:10:48.680566 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-probe-ip
173 14:10:48.681045 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-target-ip
174 14:10:48.681521 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-target-mac
175 14:10:48.681998 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-target-storage
176 14:10:48.682484 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-case
177 14:10:48.682967 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-event
178 14:10:48.683540 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-feedback
179 14:10:48.684074 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-raise
180 14:10:48.684567 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-reference
181 14:10:48.685044 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-runner
182 14:10:48.685523 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-set
183 14:10:48.685996 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-test-shell
184 14:10:48.686498 Updating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-install-packages (oe)
185 14:10:48.687045 Updating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/bin/lava-installed-packages (oe)
186 14:10:48.687486 Creating /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/environment
187 14:10:48.687873 LAVA metadata
188 14:10:48.688158 - LAVA_JOB_ID=970720
189 14:10:48.688374 - LAVA_DISPATCHER_IP=192.168.6.2
190 14:10:48.688745 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 14:10:48.689738 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 14:10:48.690053 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 14:10:48.690260 skipped lava-vland-overlay
194 14:10:48.690500 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 14:10:48.690752 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 14:10:48.690969 skipped lava-multinode-overlay
197 14:10:48.691207 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 14:10:48.691455 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 14:10:48.691699 Loading test definitions
200 14:10:48.691969 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 14:10:48.692224 Using /lava-970720 at stage 0
202 14:10:48.693380 uuid=970720_1.6.2.4.1 testdef=None
203 14:10:48.693685 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 14:10:48.693949 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 14:10:48.695799 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 14:10:48.696641 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 14:10:48.698848 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 14:10:48.699680 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 14:10:48.701820 runner path: /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 970720_1.6.2.4.1
212 14:10:48.702394 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 14:10:48.703154 Creating lava-test-runner.conf files
215 14:10:48.703352 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/970720/lava-overlay-lzwv84dd/lava-970720/0 for stage 0
216 14:10:48.703696 - 0_v4l2-decoder-conformance-h265
217 14:10:48.704081 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 14:10:48.704362 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 14:10:48.725951 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 14:10:48.726388 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 14:10:48.726649 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 14:10:48.726922 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 14:10:48.727186 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 14:10:49.351846 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 14:10:49.352435 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 14:10:49.352714 extracting modules file /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/970720/extract-nfsrootfs-t_9a5b3f
227 14:10:50.759847 extracting modules file /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/970720/extract-overlay-ramdisk-pbjgjdeg/ramdisk
228 14:10:52.151424 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 14:10:52.151929 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 14:10:52.152272 [common] Applying overlay to NFS
231 14:10:52.152515 [common] Applying overlay /var/lib/lava/dispatcher/tmp/970720/compress-overlay-vq50s5ka/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/970720/extract-nfsrootfs-t_9a5b3f
232 14:10:52.183318 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 14:10:52.183762 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 14:10:52.184105 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 14:10:52.184372 Converting downloaded kernel to a uImage
236 14:10:52.184704 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/kernel/Image /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/kernel/uImage
237 14:10:52.677072 output: Image Name:
238 14:10:52.677528 output: Created: Sun Nov 10 14:10:52 2024
239 14:10:52.677784 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 14:10:52.678017 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 14:10:52.678243 output: Load Address: 01080000
242 14:10:52.678467 output: Entry Point: 01080000
243 14:10:52.678689 output:
244 14:10:52.679068 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 14:10:52.679390 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 14:10:52.679715 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 14:10:52.680064 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 14:10:52.680386 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 14:10:52.680670 Building ramdisk /var/lib/lava/dispatcher/tmp/970720/extract-overlay-ramdisk-pbjgjdeg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/970720/extract-overlay-ramdisk-pbjgjdeg/ramdisk
250 14:10:54.843611 >> 166827 blocks
251 14:11:03.263903 Adding RAMdisk u-boot header.
252 14:11:03.264599 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/970720/extract-overlay-ramdisk-pbjgjdeg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/970720/extract-overlay-ramdisk-pbjgjdeg/ramdisk.cpio.gz.uboot
253 14:11:03.510696 output: Image Name:
254 14:11:03.511125 output: Created: Sun Nov 10 14:11:03 2024
255 14:11:03.511556 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 14:11:03.512015 output: Data Size: 23436945 Bytes = 22887.64 KiB = 22.35 MiB
257 14:11:03.512441 output: Load Address: 00000000
258 14:11:03.512844 output: Entry Point: 00000000
259 14:11:03.513245 output:
260 14:11:03.514214 rename /var/lib/lava/dispatcher/tmp/970720/extract-overlay-ramdisk-pbjgjdeg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot
261 14:11:03.514944 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 14:11:03.515502 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 14:11:03.516068 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 14:11:03.516548 No LXC device requested
265 14:11:03.517063 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 14:11:03.517587 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 14:11:03.518094 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 14:11:03.518511 Checking files for TFTP limit of 4294967296 bytes.
269 14:11:03.521221 end: 1 tftp-deploy (duration 00:01:04) [common]
270 14:11:03.521837 start: 2 uboot-action (timeout 00:05:00) [common]
271 14:11:03.522382 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 14:11:03.522888 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 14:11:03.523398 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 14:11:03.523931 Using kernel file from prepare-kernel: 970720/tftp-deploy-055hu2v5/kernel/uImage
275 14:11:03.524602 substitutions:
276 14:11:03.525020 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 14:11:03.525429 - {DTB_ADDR}: 0x01070000
278 14:11:03.525832 - {DTB}: 970720/tftp-deploy-055hu2v5/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 14:11:03.526234 - {INITRD}: 970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot
280 14:11:03.526638 - {KERNEL_ADDR}: 0x01080000
281 14:11:03.527030 - {KERNEL}: 970720/tftp-deploy-055hu2v5/kernel/uImage
282 14:11:03.527426 - {LAVA_MAC}: None
283 14:11:03.527860 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/970720/extract-nfsrootfs-t_9a5b3f
284 14:11:03.528340 - {NFS_SERVER_IP}: 192.168.6.2
285 14:11:03.528745 - {PRESEED_CONFIG}: None
286 14:11:03.529142 - {PRESEED_LOCAL}: None
287 14:11:03.529533 - {RAMDISK_ADDR}: 0x08000000
288 14:11:03.529922 - {RAMDISK}: 970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot
289 14:11:03.530312 - {ROOT_PART}: None
290 14:11:03.530726 - {ROOT}: None
291 14:11:03.531129 - {SERVER_IP}: 192.168.6.2
292 14:11:03.531524 - {TEE_ADDR}: 0x83000000
293 14:11:03.531926 - {TEE}: None
294 14:11:03.532359 Parsed boot commands:
295 14:11:03.532748 - setenv autoload no
296 14:11:03.533140 - setenv initrd_high 0xffffffff
297 14:11:03.533531 - setenv fdt_high 0xffffffff
298 14:11:03.533917 - dhcp
299 14:11:03.534303 - setenv serverip 192.168.6.2
300 14:11:03.534689 - tftpboot 0x01080000 970720/tftp-deploy-055hu2v5/kernel/uImage
301 14:11:03.535078 - tftpboot 0x08000000 970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot
302 14:11:03.535465 - tftpboot 0x01070000 970720/tftp-deploy-055hu2v5/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 14:11:03.535852 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/970720/extract-nfsrootfs-t_9a5b3f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 14:11:03.536287 - bootm 0x01080000 0x08000000 0x01070000
305 14:11:03.536807 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 14:11:03.538307 start: 2.3 connect-device (timeout 00:05:00) [common]
308 14:11:03.538736 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 14:11:03.553873 Setting prompt string to ['lava-test: # ']
310 14:11:03.555391 end: 2.3 connect-device (duration 00:00:00) [common]
311 14:11:03.556049 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 14:11:03.556627 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 14:11:03.557175 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 14:11:03.558315 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 14:11:03.598149 >> OK - accepted request
316 14:11:03.600330 Returned 0 in 0 seconds
317 14:11:03.701466 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 14:11:03.703157 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 14:11:03.703759 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 14:11:03.704354 Setting prompt string to ['Hit any key to stop autoboot']
322 14:11:03.704831 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 14:11:03.706421 Trying 192.168.56.21...
324 14:11:03.706895 Connected to conserv1.
325 14:11:03.707323 Escape character is '^]'.
326 14:11:03.707742
327 14:11:03.708200 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 14:11:03.708622
329 14:11:11.189029 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 14:11:11.189456 bl2_stage_init 0x01
331 14:11:11.189685 bl2_stage_init 0x81
332 14:11:11.194715 hw id: 0x0000 - pwm id 0x01
333 14:11:11.194996 bl2_stage_init 0xc1
334 14:11:11.198791 bl2_stage_init 0x02
335 14:11:11.199055
336 14:11:11.199276 L0:00000000
337 14:11:11.199499 L1:00000703
338 14:11:11.199706 L2:00008067
339 14:11:11.204338 L3:15000000
340 14:11:11.204618 S1:00000000
341 14:11:11.204843 B2:20282000
342 14:11:11.205054 B1:a0f83180
343 14:11:11.205266
344 14:11:11.205477 TE: 68782
345 14:11:11.209939
346 14:11:11.214973 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 14:11:11.215239
348 14:11:11.215451 Board ID = 1
349 14:11:11.215657 Set cpu clk to 24M
350 14:11:11.220650 Set clk81 to 24M
351 14:11:11.220923 Use GP1_pll as DSU clk.
352 14:11:11.221140 DSU clk: 1200 Mhz
353 14:11:11.221349 CPU clk: 1200 MHz
354 14:11:11.226240 Set clk81 to 166.6M
355 14:11:11.231850 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 14:11:11.232153 board id: 1
357 14:11:11.240452 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 14:11:11.251328 fw parse done
359 14:11:11.257275 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 14:11:11.300360 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 14:11:11.311438 PIEI prepare done
362 14:11:11.311734 fastboot data load
363 14:11:11.311951 fastboot data verify
364 14:11:11.317161 verify result: 266
365 14:11:11.322716 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 14:11:11.322991 LPDDR4 probe
367 14:11:11.323207 ddr clk to 1584MHz
368 14:11:11.330746 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 14:11:11.368489
370 14:11:11.368840 dmc_version 0001
371 14:11:11.375570 Check phy result
372 14:11:11.381490 INFO : End of CA training
373 14:11:11.381798 INFO : End of initialization
374 14:11:11.387063 INFO : Training has run successfully!
375 14:11:11.387464 Check phy result
376 14:11:11.392636 INFO : End of initialization
377 14:11:11.392919 INFO : End of read enable training
378 14:11:11.398256 INFO : End of fine write leveling
379 14:11:11.403896 INFO : End of Write leveling coarse delay
380 14:11:11.404232 INFO : Training has run successfully!
381 14:11:11.404454 Check phy result
382 14:11:11.409480 INFO : End of initialization
383 14:11:11.409885 INFO : End of read dq deskew training
384 14:11:11.415153 INFO : End of MPR read delay center optimization
385 14:11:11.420664 INFO : End of write delay center optimization
386 14:11:11.426287 INFO : End of read delay center optimization
387 14:11:11.426572 INFO : End of max read latency training
388 14:11:11.431909 INFO : Training has run successfully!
389 14:11:11.432329 1D training succeed
390 14:11:11.441096 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 14:11:11.489468 Check phy result
392 14:11:11.489895 INFO : End of initialization
393 14:11:11.521451 INFO : End of 2D read delay Voltage center optimization
394 14:11:11.541017 INFO : End of 2D read delay Voltage center optimization
395 14:11:11.597619 INFO : End of 2D write delay Voltage center optimization
396 14:11:11.651467 INFO : End of 2D write delay Voltage center optimization
397 14:11:11.657137 INFO : Training has run successfully!
398 14:11:11.657595
399 14:11:11.658015 channel==0
400 14:11:11.662673 RxClkDly_Margin_A0==78 ps 8
401 14:11:11.663110 TxDqDly_Margin_A0==98 ps 10
402 14:11:11.668311 RxClkDly_Margin_A1==88 ps 9
403 14:11:11.668752 TxDqDly_Margin_A1==98 ps 10
404 14:11:11.669153 TrainedVREFDQ_A0==74
405 14:11:11.673881 TrainedVREFDQ_A1==75
406 14:11:11.674316 VrefDac_Margin_A0==23
407 14:11:11.674713 DeviceVref_Margin_A0==40
408 14:11:11.679389 VrefDac_Margin_A1==23
409 14:11:11.679809 DeviceVref_Margin_A1==39
410 14:11:11.680244
411 14:11:11.680635
412 14:11:11.685084 channel==1
413 14:11:11.685514 RxClkDly_Margin_A0==88 ps 9
414 14:11:11.685910 TxDqDly_Margin_A0==98 ps 10
415 14:11:11.690632 RxClkDly_Margin_A1==78 ps 8
416 14:11:11.691057 TxDqDly_Margin_A1==78 ps 8
417 14:11:11.696288 TrainedVREFDQ_A0==78
418 14:11:11.696711 TrainedVREFDQ_A1==77
419 14:11:11.697103 VrefDac_Margin_A0==23
420 14:11:11.701805 DeviceVref_Margin_A0==36
421 14:11:11.702232 VrefDac_Margin_A1==22
422 14:11:11.707454 DeviceVref_Margin_A1==37
423 14:11:11.707878
424 14:11:11.708307 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 14:11:11.708698
426 14:11:11.740931 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
427 14:11:11.741463 2D training succeed
428 14:11:11.746553 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 14:11:11.752189 auto size-- 65535DDR cs0 size: 2048MB
430 14:11:11.752611 DDR cs1 size: 2048MB
431 14:11:11.757766 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 14:11:11.758188 cs0 DataBus test pass
433 14:11:11.763355 cs1 DataBus test pass
434 14:11:11.763776 cs0 AddrBus test pass
435 14:11:11.764202 cs1 AddrBus test pass
436 14:11:11.764590
437 14:11:11.768932 100bdlr_step_size ps== 478
438 14:11:11.769362 result report
439 14:11:11.774526 boot times 0Enable ddr reg access
440 14:11:11.779794 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 14:11:11.793735 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 14:11:12.453003 bl2z: ptr: 05129330, size: 00001e40
443 14:11:12.461417 0.0;M3 CHK:0;cm4_sp_mode 0
444 14:11:12.461875 MVN_1=0x00000000
445 14:11:12.462274 MVN_2=0x00000000
446 14:11:12.472952 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 14:11:12.473421 OPS=0x04
448 14:11:12.473822 ring efuse init
449 14:11:12.475871 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 14:11:12.482380 [0.017354 Inits done]
451 14:11:12.482838 secure task start!
452 14:11:12.483231 high task start!
453 14:11:12.483619 low task start!
454 14:11:12.487613 run into bl31
455 14:11:12.495285 NOTICE: BL31: v1.3(release):4fc40b1
456 14:11:12.503478 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 14:11:12.504191 NOTICE: BL31: G12A normal boot!
458 14:11:12.519352 NOTICE: BL31: BL33 decompress pass
459 14:11:12.524648 ERROR: Error initializing runtime service opteed_fast
460 14:11:15.237428 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 14:11:15.238094 bl2_stage_init 0x01
462 14:11:15.238576 bl2_stage_init 0x81
463 14:11:15.243126 hw id: 0x0000 - pwm id 0x01
464 14:11:15.243644 bl2_stage_init 0xc1
465 14:11:15.248639 bl2_stage_init 0x02
466 14:11:15.249187
467 14:11:15.249631 L0:00000000
468 14:11:15.250063 L1:00000703
469 14:11:15.250499 L2:00008067
470 14:11:15.250925 L3:15000000
471 14:11:15.254193 S1:00000000
472 14:11:15.254666 B2:20282000
473 14:11:15.255095 B1:a0f83180
474 14:11:15.255518
475 14:11:15.255944 TE: 68102
476 14:11:15.256423
477 14:11:15.260074 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 14:11:15.260544
479 14:11:15.265366 Board ID = 1
480 14:11:15.265830 Set cpu clk to 24M
481 14:11:15.266260 Set clk81 to 24M
482 14:11:15.271032 Use GP1_pll as DSU clk.
483 14:11:15.271508 DSU clk: 1200 Mhz
484 14:11:15.271938 CPU clk: 1200 MHz
485 14:11:15.276652 Set clk81 to 166.6M
486 14:11:15.282230 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 14:11:15.282695 board id: 1
488 14:11:15.289385 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 14:11:15.300136 fw parse done
490 14:11:15.306054 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 14:11:15.348686 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 14:11:15.359559 PIEI prepare done
493 14:11:15.360051 fastboot data load
494 14:11:15.360487 fastboot data verify
495 14:11:15.365301 verify result: 266
496 14:11:15.370849 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 14:11:15.371336 LPDDR4 probe
498 14:11:15.371765 ddr clk to 1584MHz
499 14:11:15.378822 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
500 14:11:15.416166
501 14:11:15.416704 dmc_version 0001
502 14:11:15.422807 Check phy result
503 14:11:15.428781 INFO : End of CA training
504 14:11:15.429305 INFO : End of initialization
505 14:11:15.434294 INFO : Training has run successfully!
506 14:11:15.434790 Check phy result
507 14:11:15.439921 INFO : End of initialization
508 14:11:15.440446 INFO : End of read enable training
509 14:11:15.445532 INFO : End of fine write leveling
510 14:11:15.451131 INFO : End of Write leveling coarse delay
511 14:11:15.451631 INFO : Training has run successfully!
512 14:11:15.452131 Check phy result
513 14:11:15.456733 INFO : End of initialization
514 14:11:15.457225 INFO : End of read dq deskew training
515 14:11:15.462323 INFO : End of MPR read delay center optimization
516 14:11:15.467917 INFO : End of write delay center optimization
517 14:11:15.473507 INFO : End of read delay center optimization
518 14:11:15.474004 INFO : End of max read latency training
519 14:11:15.479143 INFO : Training has run successfully!
520 14:11:15.479660 1D training succeed
521 14:11:15.488286 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
522 14:11:15.535923 Check phy result
523 14:11:15.536512 INFO : End of initialization
524 14:11:15.558308 INFO : End of 2D read delay Voltage center optimization
525 14:11:15.577454 INFO : End of 2D read delay Voltage center optimization
526 14:11:15.629324 INFO : End of 2D write delay Voltage center optimization
527 14:11:15.678508 INFO : End of 2D write delay Voltage center optimization
528 14:11:15.684080 INFO : Training has run successfully!
529 14:11:15.684579
530 14:11:15.685033 channel==0
531 14:11:15.689673 RxClkDly_Margin_A0==78 ps 8
532 14:11:15.690167 TxDqDly_Margin_A0==88 ps 9
533 14:11:15.695219 RxClkDly_Margin_A1==88 ps 9
534 14:11:15.695707 TxDqDly_Margin_A1==98 ps 10
535 14:11:15.696199 TrainedVREFDQ_A0==74
536 14:11:15.701066 TrainedVREFDQ_A1==74
537 14:11:15.701561 VrefDac_Margin_A0==24
538 14:11:15.702012 DeviceVref_Margin_A0==40
539 14:11:15.706441 VrefDac_Margin_A1==23
540 14:11:15.706932 DeviceVref_Margin_A1==40
541 14:11:15.707378
542 14:11:15.707818
543 14:11:15.708301 channel==1
544 14:11:15.712165 RxClkDly_Margin_A0==78 ps 8
545 14:11:15.712660 TxDqDly_Margin_A0==98 ps 10
546 14:11:15.717628 RxClkDly_Margin_A1==88 ps 9
547 14:11:15.718126 TxDqDly_Margin_A1==88 ps 9
548 14:11:15.723333 TrainedVREFDQ_A0==78
549 14:11:15.723843 TrainedVREFDQ_A1==75
550 14:11:15.724332 VrefDac_Margin_A0==22
551 14:11:15.728878 DeviceVref_Margin_A0==36
552 14:11:15.729374 VrefDac_Margin_A1==22
553 14:11:15.734612 DeviceVref_Margin_A1==39
554 14:11:15.735113
555 14:11:15.735566 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
556 14:11:15.736040
557 14:11:15.767973 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
558 14:11:15.768537 2D training succeed
559 14:11:15.773636 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
560 14:11:15.779230 auto size-- 65535DDR cs0 size: 2048MB
561 14:11:15.779727 DDR cs1 size: 2048MB
562 14:11:15.784819 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
563 14:11:15.785314 cs0 DataBus test pass
564 14:11:15.790591 cs1 DataBus test pass
565 14:11:15.791111 cs0 AddrBus test pass
566 14:11:15.791564 cs1 AddrBus test pass
567 14:11:15.792048
568 14:11:15.795969 100bdlr_step_size ps== 478
569 14:11:15.796472 result report
570 14:11:15.801554 boot times 0Enable ddr reg access
571 14:11:15.806731 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
572 14:11:15.820564 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
573 14:11:16.474764 bl2z: ptr: 05129330, size: 00001e40
574 14:11:16.482383 0.0;M3 CHK:0;cm4_sp_mode 0
575 14:11:16.482893 MVN_1=0x00000000
576 14:11:16.483348 MVN_2=0x00000000
577 14:11:16.493901 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
578 14:11:16.494395 OPS=0x04
579 14:11:16.494846 ring efuse init
580 14:11:16.499486 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
581 14:11:16.499977 [0.017319 Inits done]
582 14:11:16.500484 secure task start!
583 14:11:16.506668 high task start!
584 14:11:16.507160 low task start!
585 14:11:16.507608 run into bl31
586 14:11:16.515251 NOTICE: BL31: v1.3(release):4fc40b1
587 14:11:16.523063 NOTICE: BL31: Built : 15:57:33, May 22 2019
588 14:11:16.523561 NOTICE: BL31: G12A normal boot!
589 14:11:16.538582 NOTICE: BL31: BL33 decompress pass
590 14:11:16.544244 ERROR: Error initializing runtime service opteed_fast
591 14:11:17.939753 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
592 14:11:17.940449 bl2_stage_init 0x01
593 14:11:17.940917 bl2_stage_init 0x81
594 14:11:17.945123 hw id: 0x0000 - pwm id 0x01
595 14:11:17.945608 bl2_stage_init 0xc1
596 14:11:17.950773 bl2_stage_init 0x02
597 14:11:17.951247
598 14:11:17.951703 L0:00000000
599 14:11:17.952229 L1:00000703
600 14:11:17.952693 L2:00008067
601 14:11:17.953134 L3:15000000
602 14:11:17.956325 S1:00000000
603 14:11:17.956810 B2:20282000
604 14:11:17.957258 B1:a0f83180
605 14:11:17.957698
606 14:11:17.958138 TE: 69792
607 14:11:17.958573
608 14:11:17.961883 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
609 14:11:17.962360
610 14:11:17.967604 Board ID = 1
611 14:11:17.968115 Set cpu clk to 24M
612 14:11:17.968566 Set clk81 to 24M
613 14:11:17.973075 Use GP1_pll as DSU clk.
614 14:11:17.973550 DSU clk: 1200 Mhz
615 14:11:17.973993 CPU clk: 1200 MHz
616 14:11:17.978761 Set clk81 to 166.6M
617 14:11:17.984389 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
618 14:11:17.984864 board id: 1
619 14:11:17.991826 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
620 14:11:18.002067 fw parse done
621 14:11:18.008065 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
622 14:11:18.050659 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
623 14:11:18.061631 PIEI prepare done
624 14:11:18.062132 fastboot data load
625 14:11:18.062590 fastboot data verify
626 14:11:18.067203 verify result: 266
627 14:11:18.072796 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
628 14:11:18.073284 LPDDR4 probe
629 14:11:18.073737 ddr clk to 1584MHz
630 14:11:18.080783 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
631 14:11:18.118159
632 14:11:18.118653 dmc_version 0001
633 14:11:18.124728 Check phy result
634 14:11:18.130653 INFO : End of CA training
635 14:11:18.131123 INFO : End of initialization
636 14:11:18.136272 INFO : Training has run successfully!
637 14:11:18.136745 Check phy result
638 14:11:18.141844 INFO : End of initialization
639 14:11:18.142313 INFO : End of read enable training
640 14:11:18.147432 INFO : End of fine write leveling
641 14:11:18.153045 INFO : End of Write leveling coarse delay
642 14:11:18.153517 INFO : Training has run successfully!
643 14:11:18.153961 Check phy result
644 14:11:18.158691 INFO : End of initialization
645 14:11:18.159158 INFO : End of read dq deskew training
646 14:11:18.164251 INFO : End of MPR read delay center optimization
647 14:11:18.169821 INFO : End of write delay center optimization
648 14:11:18.175531 INFO : End of read delay center optimization
649 14:11:18.176039 INFO : End of max read latency training
650 14:11:18.181047 INFO : Training has run successfully!
651 14:11:18.181530 1D training succeed
652 14:11:18.190217 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
653 14:11:18.237903 Check phy result
654 14:11:18.238378 INFO : End of initialization
655 14:11:18.260230 INFO : End of 2D read delay Voltage center optimization
656 14:11:18.279320 INFO : End of 2D read delay Voltage center optimization
657 14:11:18.331353 INFO : End of 2D write delay Voltage center optimization
658 14:11:18.380362 INFO : End of 2D write delay Voltage center optimization
659 14:11:18.385978 INFO : Training has run successfully!
660 14:11:18.386279
661 14:11:18.386534 channel==0
662 14:11:18.391537 RxClkDly_Margin_A0==78 ps 8
663 14:11:18.391813 TxDqDly_Margin_A0==88 ps 9
664 14:11:18.397131 RxClkDly_Margin_A1==88 ps 9
665 14:11:18.397398 TxDqDly_Margin_A1==98 ps 10
666 14:11:18.397637 TrainedVREFDQ_A0==74
667 14:11:18.402734 TrainedVREFDQ_A1==75
668 14:11:18.403018 VrefDac_Margin_A0==25
669 14:11:18.403258 DeviceVref_Margin_A0==40
670 14:11:18.408360 VrefDac_Margin_A1==23
671 14:11:18.408715 DeviceVref_Margin_A1==39
672 14:11:18.409324
673 14:11:18.409971
674 14:11:18.410347 channel==1
675 14:11:18.413923 RxClkDly_Margin_A0==78 ps 8
676 14:11:18.414325 TxDqDly_Margin_A0==88 ps 9
677 14:11:18.419549 RxClkDly_Margin_A1==78 ps 8
678 14:11:18.419937 TxDqDly_Margin_A1==98 ps 10
679 14:11:18.425106 TrainedVREFDQ_A0==75
680 14:11:18.425382 TrainedVREFDQ_A1==78
681 14:11:18.425624 VrefDac_Margin_A0==22
682 14:11:18.430725 DeviceVref_Margin_A0==39
683 14:11:18.431006 VrefDac_Margin_A1==22
684 14:11:18.436319 DeviceVref_Margin_A1==36
685 14:11:18.436688
686 14:11:18.437194 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
687 14:11:18.437901
688 14:11:18.469911 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
689 14:11:18.470215 2D training succeed
690 14:11:18.475542 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
691 14:11:18.481141 auto size-- 65535DDR cs0 size: 2048MB
692 14:11:18.481406 DDR cs1 size: 2048MB
693 14:11:18.486693 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
694 14:11:18.486959 cs0 DataBus test pass
695 14:11:18.492311 cs1 DataBus test pass
696 14:11:18.492603 cs0 AddrBus test pass
697 14:11:18.492840 cs1 AddrBus test pass
698 14:11:18.493072
699 14:11:18.497908 100bdlr_step_size ps== 478
700 14:11:18.498189 result report
701 14:11:18.503546 boot times 0Enable ddr reg access
702 14:11:18.508710 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
703 14:11:18.522633 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
704 14:11:19.177542 bl2z: ptr: 05129330, size: 00001e40
705 14:11:19.184619 0.0;M3 CHK:0;cm4_sp_mode 0
706 14:11:19.185007 MVN_1=0x00000000
707 14:11:19.185298 MVN_2=0x00000000
708 14:11:19.196074 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
709 14:11:19.196447 OPS=0x04
710 14:11:19.196771 ring efuse init
711 14:11:19.201680 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
712 14:11:19.202051 [0.017319 Inits done]
713 14:11:19.202330 secure task start!
714 14:11:19.209673 high task start!
715 14:11:19.210034 low task start!
716 14:11:19.210312 run into bl31
717 14:11:19.218303 NOTICE: BL31: v1.3(release):4fc40b1
718 14:11:19.226127 NOTICE: BL31: Built : 15:57:33, May 22 2019
719 14:11:19.226495 NOTICE: BL31: G12A normal boot!
720 14:11:19.241644 NOTICE: BL31: BL33 decompress pass
721 14:11:19.247328 ERROR: Error initializing runtime service opteed_fast
722 14:11:20.042960
723 14:11:20.043656
724 14:11:20.048271 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
725 14:11:20.048852
726 14:11:20.051822 Model: Libre Computer AML-S905D3-CC Solitude
727 14:11:20.198888 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
728 14:11:20.214182 DRAM: 2 GiB (effective 3.8 GiB)
729 14:11:20.315206 Core: 406 devices, 33 uclasses, devicetree: separate
730 14:11:20.321575 WDT: Not starting watchdog@f0d0
731 14:11:20.346140 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
732 14:11:20.358339 Loading Environment from FAT... Card did not respond to voltage select! : -110
733 14:11:20.363296 ** Bad device specification mmc 0 **
734 14:11:20.373437 Card did not respond to voltage select! : -110
735 14:11:20.381037 ** Bad device specification mmc 0 **
736 14:11:20.381798 Couldn't find partition mmc 0
737 14:11:20.389388 Card did not respond to voltage select! : -110
738 14:11:20.394958 ** Bad device specification mmc 0 **
739 14:11:20.395694 Couldn't find partition mmc 0
740 14:11:20.399948 Error: could not access storage.
741 14:11:20.696433 Net: eth0: ethernet@ff3f0000
742 14:11:20.697340 starting USB...
743 14:11:20.941222 Bus usb@ff500000: Register 3000140 NbrPorts 3
744 14:11:20.942090 Starting the controller
745 14:11:20.948076 USB XHCI 1.10
746 14:11:22.502318 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
747 14:11:22.510502 scanning usb for storage devices... 0 Storage Device(s) found
749 14:11:22.562096 Hit any key to stop autoboot: 1
750 14:11:22.562955 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
751 14:11:22.563597 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
752 14:11:22.564157 Setting prompt string to ['=>']
753 14:11:22.564679 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
754 14:11:22.576572 0
755 14:11:22.577529 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
757 14:11:22.678809 => setenv autoload no
758 14:11:22.679470 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
759 14:11:22.684740 setenv autoload no
761 14:11:22.786249 => setenv initrd_high 0xffffffff
762 14:11:22.786884 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
763 14:11:22.791112 setenv initrd_high 0xffffffff
765 14:11:22.892609 => setenv fdt_high 0xffffffff
766 14:11:22.893213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
767 14:11:22.897483 setenv fdt_high 0xffffffff
769 14:11:22.998987 => dhcp
770 14:11:22.999667 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
771 14:11:23.003839 dhcp
772 14:11:23.559327 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
773 14:11:23.559935 Speed: 1000, full duplex
774 14:11:23.560421 BOOTP broadcast 1
775 14:11:23.592189 DHCP client bound to address 192.168.6.21 (32 ms)
777 14:11:23.693693 => setenv serverip 192.168.6.2
778 14:11:23.694317 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
779 14:11:23.698785 setenv serverip 192.168.6.2
781 14:11:23.800212 => tftpboot 0x01080000 970720/tftp-deploy-055hu2v5/kernel/uImage
782 14:11:23.800836 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
783 14:11:23.807630 tftpboot 0x01080000 970720/tftp-deploy-055hu2v5/kernel/uImage
784 14:11:23.808146 Speed: 1000, full duplex
785 14:11:23.808588 Using ethernet@ff3f0000 device
786 14:11:23.813149 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
787 14:11:23.818614 Filename '970720/tftp-deploy-055hu2v5/kernel/uImage'.
788 14:11:23.822521 Load address: 0x1080000
789 14:11:24.287523 Loading: *######## UDP wrong checksum 000000ff 0000713e
790 14:11:24.329007 # UDP wrong checksum 000000ff 00000231
791 14:11:26.560987 ######################################### 43.6 MiB
792 14:11:26.561603 15.9 MiB/s
793 14:11:26.562032 done
794 14:11:26.565579 Bytes transferred = 45713984 (2b98a40 hex)
796 14:11:26.667183 => tftpboot 0x08000000 970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot
797 14:11:26.667902 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
798 14:11:26.674709 tftpboot 0x08000000 970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot
799 14:11:26.675169 Speed: 1000, full duplex
800 14:11:26.675561 Using ethernet@ff3f0000 device
801 14:11:26.680326 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 14:11:26.690122 Filename '970720/tftp-deploy-055hu2v5/ramdisk/ramdisk.cpio.gz.uboot'.
803 14:11:26.690604 Load address: 0x8000000
804 14:11:28.105133 Loading: *################################################# UDP wrong checksum 00000005 0000b16f
805 14:11:32.898899 UDP wrong checksum 000000ff 00004898
806 14:11:32.939040 UDP wrong checksum 000000ff 0000a122
807 14:11:33.104844 T UDP wrong checksum 00000005 0000b16f
808 14:11:43.106777 T T UDP wrong checksum 00000005 0000b16f
809 14:12:03.110824 T T T T UDP wrong checksum 00000005 0000b16f
810 14:12:10.760942 T UDP wrong checksum 000000ff 000040de
811 14:12:10.768808 UDP wrong checksum 000000ff 00009962
812 14:12:23.115749 T T
813 14:12:23.116411 Retry count exceeded; starting again
815 14:12:23.117833 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
818 14:12:23.119687 end: 2.4 uboot-commands (duration 00:01:20) [common]
820 14:12:23.121121 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 14:12:23.122119 end: 2 uboot-action (duration 00:01:20) [common]
824 14:12:23.123589 Cleaning after the job
825 14:12:23.124150 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/ramdisk
826 14:12:23.125540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/kernel
827 14:12:23.172211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/dtb
828 14:12:23.172992 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/nfsrootfs
829 14:12:23.488980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970720/tftp-deploy-055hu2v5/modules
830 14:12:23.510081 start: 4.1 power-off (timeout 00:00:30) [common]
831 14:12:23.510767 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
832 14:12:23.544726 >> OK - accepted request
833 14:12:23.547332 Returned 0 in 0 seconds
834 14:12:23.648107 end: 4.1 power-off (duration 00:00:00) [common]
836 14:12:23.649101 start: 4.2 read-feedback (timeout 00:10:00) [common]
837 14:12:23.649763 Listened to connection for namespace 'common' for up to 1s
838 14:12:24.649904 Finalising connection for namespace 'common'
839 14:12:24.650386 Disconnecting from shell: Finalise
840 14:12:24.650674 =>
841 14:12:24.751433 end: 4.2 read-feedback (duration 00:00:01) [common]
842 14:12:24.752093 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/970720
843 14:12:27.287093 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/970720
844 14:12:27.287700 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.