Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 12:01:37.353790 lava-dispatcher, installed at version: 2024.01
2 12:01:37.354611 start: 0 validate
3 12:01:37.355064 Start time: 2024-11-04 12:01:37.355035+00:00 (UTC)
4 12:01:37.355578 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:01:37.356871 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 12:01:37.397637 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:01:37.398197 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fulfh%2Fnext%2Fmmc-v6.12-rc3-75-g84185573da38%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 12:01:37.430075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:01:37.431033 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fulfh%2Fnext%2Fmmc-v6.12-rc3-75-g84185573da38%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 12:01:44.504708 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:01:44.505231 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fulfh%2Fnext%2Fmmc-v6.12-rc3-75-g84185573da38%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 12:01:44.540985 validate duration: 7.19
14 12:01:44.541804 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:01:44.542138 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:01:44.542440 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:01:44.543018 Not decompressing ramdisk as can be used compressed.
18 12:01:44.543396 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 12:01:44.543630 saving as /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/ramdisk/rootfs.cpio.gz
20 12:01:44.543886 total size: 8181887 (7 MB)
21 12:01:44.580102 progress 0 % (0 MB)
22 12:01:44.586899 progress 5 % (0 MB)
23 12:01:44.593037 progress 10 % (0 MB)
24 12:01:44.598878 progress 15 % (1 MB)
25 12:01:44.604819 progress 20 % (1 MB)
26 12:01:44.610439 progress 25 % (1 MB)
27 12:01:44.615632 progress 30 % (2 MB)
28 12:01:44.621238 progress 35 % (2 MB)
29 12:01:44.626418 progress 40 % (3 MB)
30 12:01:44.631907 progress 45 % (3 MB)
31 12:01:44.637109 progress 50 % (3 MB)
32 12:01:44.642712 progress 55 % (4 MB)
33 12:01:44.647901 progress 60 % (4 MB)
34 12:01:44.653461 progress 65 % (5 MB)
35 12:01:44.658696 progress 70 % (5 MB)
36 12:01:44.664243 progress 75 % (5 MB)
37 12:01:44.669317 progress 80 % (6 MB)
38 12:01:44.674723 progress 85 % (6 MB)
39 12:01:44.679557 progress 90 % (7 MB)
40 12:01:44.684809 progress 95 % (7 MB)
41 12:01:44.689578 progress 100 % (7 MB)
42 12:01:44.690230 7 MB downloaded in 0.15 s (53.33 MB/s)
43 12:01:44.690789 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:01:44.691685 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:01:44.692003 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:01:44.692345 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:01:44.692863 downloading http://storage.kernelci.org/ulfh/next/mmc-v6.12-rc3-75-g84185573da38/arm64/defconfig/gcc-12/kernel/Image
49 12:01:44.693140 saving as /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/kernel/Image
50 12:01:44.693361 total size: 45713920 (43 MB)
51 12:01:44.693588 No compression specified
52 12:01:44.727738 progress 0 % (0 MB)
53 12:01:44.756315 progress 5 % (2 MB)
54 12:01:44.784443 progress 10 % (4 MB)
55 12:01:44.812682 progress 15 % (6 MB)
56 12:01:44.840536 progress 20 % (8 MB)
57 12:01:44.868207 progress 25 % (10 MB)
58 12:01:44.895685 progress 30 % (13 MB)
59 12:01:44.923130 progress 35 % (15 MB)
60 12:01:44.950418 progress 40 % (17 MB)
61 12:01:44.977362 progress 45 % (19 MB)
62 12:01:45.004393 progress 50 % (21 MB)
63 12:01:45.031512 progress 55 % (24 MB)
64 12:01:45.058776 progress 60 % (26 MB)
65 12:01:45.085477 progress 65 % (28 MB)
66 12:01:45.112482 progress 70 % (30 MB)
67 12:01:45.139833 progress 75 % (32 MB)
68 12:01:45.167063 progress 80 % (34 MB)
69 12:01:45.193716 progress 85 % (37 MB)
70 12:01:45.220722 progress 90 % (39 MB)
71 12:01:45.247747 progress 95 % (41 MB)
72 12:01:45.274052 progress 100 % (43 MB)
73 12:01:45.274614 43 MB downloaded in 0.58 s (75.01 MB/s)
74 12:01:45.275104 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:01:45.275918 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:01:45.276217 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:01:45.276481 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:01:45.276953 downloading http://storage.kernelci.org/ulfh/next/mmc-v6.12-rc3-75-g84185573da38/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 12:01:45.277224 saving as /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/dtb/meson-g12b-a311d-libretech-cc.dtb
81 12:01:45.277431 total size: 54703 (0 MB)
82 12:01:45.277640 No compression specified
83 12:01:45.316393 progress 59 % (0 MB)
84 12:01:45.317242 progress 100 % (0 MB)
85 12:01:45.317776 0 MB downloaded in 0.04 s (1.29 MB/s)
86 12:01:45.318263 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:01:45.319070 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:01:45.319326 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:01:45.319583 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:01:45.320070 downloading http://storage.kernelci.org/ulfh/next/mmc-v6.12-rc3-75-g84185573da38/arm64/defconfig/gcc-12/modules.tar.xz
92 12:01:45.320319 saving as /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/modules/modules.tar
93 12:01:45.320523 total size: 11606276 (11 MB)
94 12:01:45.320732 Using unxz to decompress xz
95 12:01:45.354962 progress 0 % (0 MB)
96 12:01:45.425294 progress 5 % (0 MB)
97 12:01:45.502796 progress 10 % (1 MB)
98 12:01:45.601685 progress 15 % (1 MB)
99 12:01:45.695140 progress 20 % (2 MB)
100 12:01:45.774586 progress 25 % (2 MB)
101 12:01:45.850679 progress 30 % (3 MB)
102 12:01:45.925306 progress 35 % (3 MB)
103 12:01:46.003317 progress 40 % (4 MB)
104 12:01:46.079533 progress 45 % (5 MB)
105 12:01:46.164084 progress 50 % (5 MB)
106 12:01:46.241616 progress 55 % (6 MB)
107 12:01:46.329265 progress 60 % (6 MB)
108 12:01:46.411334 progress 65 % (7 MB)
109 12:01:46.489328 progress 70 % (7 MB)
110 12:01:46.572999 progress 75 % (8 MB)
111 12:01:46.658499 progress 80 % (8 MB)
112 12:01:46.739001 progress 85 % (9 MB)
113 12:01:46.818462 progress 90 % (9 MB)
114 12:01:46.896900 progress 95 % (10 MB)
115 12:01:46.975447 progress 100 % (11 MB)
116 12:01:46.986444 11 MB downloaded in 1.67 s (6.64 MB/s)
117 12:01:46.987070 end: 1.4.1 http-download (duration 00:00:02) [common]
119 12:01:46.987906 end: 1.4 download-retry (duration 00:00:02) [common]
120 12:01:46.988469 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:01:46.989087 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:01:46.989650 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:01:46.990207 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:01:46.991408 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c
125 12:01:46.992403 makedir: /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin
126 12:01:46.993175 makedir: /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/tests
127 12:01:46.993862 makedir: /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/results
128 12:01:46.994536 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-add-keys
129 12:01:46.995585 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-add-sources
130 12:01:46.996702 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-background-process-start
131 12:01:46.997819 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-background-process-stop
132 12:01:46.998920 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-common-functions
133 12:01:46.999920 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-echo-ipv4
134 12:01:47.001022 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-install-packages
135 12:01:47.002030 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-installed-packages
136 12:01:47.002998 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-os-build
137 12:01:47.004058 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-probe-channel
138 12:01:47.005137 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-probe-ip
139 12:01:47.006162 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-target-ip
140 12:01:47.007151 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-target-mac
141 12:01:47.008172 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-target-storage
142 12:01:47.009266 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-case
143 12:01:47.010274 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-event
144 12:01:47.011246 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-feedback
145 12:01:47.012288 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-raise
146 12:01:47.013370 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-reference
147 12:01:47.014371 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-runner
148 12:01:47.015372 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-set
149 12:01:47.016388 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-test-shell
150 12:01:47.017505 Updating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-install-packages (oe)
151 12:01:47.018571 Updating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/bin/lava-installed-packages (oe)
152 12:01:47.019479 Creating /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/environment
153 12:01:47.020330 LAVA metadata
154 12:01:47.020922 - LAVA_JOB_ID=933881
155 12:01:47.021418 - LAVA_DISPATCHER_IP=192.168.6.2
156 12:01:47.022184 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 12:01:47.024238 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 12:01:47.024870 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 12:01:47.025297 skipped lava-vland-overlay
160 12:01:47.025790 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 12:01:47.026295 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 12:01:47.026723 skipped lava-multinode-overlay
163 12:01:47.027207 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 12:01:47.027705 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 12:01:47.028379 Loading test definitions
166 12:01:47.029043 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 12:01:47.029496 Using /lava-933881 at stage 0
168 12:01:47.032298 uuid=933881_1.5.2.4.1 testdef=None
169 12:01:47.032712 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 12:01:47.032987 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 12:01:47.034899 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 12:01:47.035736 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 12:01:47.038117 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 12:01:47.038999 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 12:01:47.041273 runner path: /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/0/tests/0_dmesg test_uuid 933881_1.5.2.4.1
178 12:01:47.041903 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 12:01:47.042712 Creating lava-test-runner.conf files
181 12:01:47.042917 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933881/lava-overlay-zdk11_2c/lava-933881/0 for stage 0
182 12:01:47.043271 - 0_dmesg
183 12:01:47.043657 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 12:01:47.043958 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 12:01:47.079784 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 12:01:47.080291 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 12:01:47.080588 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 12:01:47.080865 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 12:01:47.081144 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 12:01:48.025680 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 12:01:48.026151 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 12:01:48.026397 extracting modules file /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk
193 12:01:49.379576 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 12:01:49.380101 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 12:01:49.380384 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933881/compress-overlay-vb801rk2/overlay-1.5.2.5.tar.gz to ramdisk
196 12:01:49.380600 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933881/compress-overlay-vb801rk2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk
197 12:01:49.410823 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 12:01:49.411277 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 12:01:49.411549 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 12:01:49.411777 Converting downloaded kernel to a uImage
201 12:01:49.412108 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/kernel/Image /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/kernel/uImage
202 12:01:49.907839 output: Image Name:
203 12:01:49.908295 output: Created: Mon Nov 4 12:01:49 2024
204 12:01:49.908522 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 12:01:49.908734 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 12:01:49.908937 output: Load Address: 01080000
207 12:01:49.909137 output: Entry Point: 01080000
208 12:01:49.909338 output:
209 12:01:49.909677 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 12:01:49.909951 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 12:01:49.910233 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 12:01:49.910494 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 12:01:49.910756 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 12:01:49.911016 Building ramdisk /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk
215 12:01:52.497162 >> 181564 blocks
216 12:02:00.916352 Adding RAMdisk u-boot header.
217 12:02:00.916807 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk.cpio.gz.uboot
218 12:02:01.186339 output: Image Name:
219 12:02:01.186755 output: Created: Mon Nov 4 12:02:00 2024
220 12:02:01.186960 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 12:02:01.187161 output: Data Size: 26058989 Bytes = 25448.23 KiB = 24.85 MiB
222 12:02:01.187360 output: Load Address: 00000000
223 12:02:01.187557 output: Entry Point: 00000000
224 12:02:01.187755 output:
225 12:02:01.188701 rename /var/lib/lava/dispatcher/tmp/933881/extract-overlay-ramdisk-0kuf9ddb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot
226 12:02:01.189505 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 12:02:01.190095 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 12:02:01.190665 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 12:02:01.191161 No LXC device requested
230 12:02:01.191705 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 12:02:01.192291 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 12:02:01.192832 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 12:02:01.193277 Checking files for TFTP limit of 4294967296 bytes.
234 12:02:01.196210 end: 1 tftp-deploy (duration 00:00:17) [common]
235 12:02:01.196838 start: 2 uboot-action (timeout 00:05:00) [common]
236 12:02:01.197405 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 12:02:01.197950 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 12:02:01.198497 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 12:02:01.199081 Using kernel file from prepare-kernel: 933881/tftp-deploy-25s6olht/kernel/uImage
240 12:02:01.199762 substitutions:
241 12:02:01.200252 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 12:02:01.200698 - {DTB_ADDR}: 0x01070000
243 12:02:01.201138 - {DTB}: 933881/tftp-deploy-25s6olht/dtb/meson-g12b-a311d-libretech-cc.dtb
244 12:02:01.201576 - {INITRD}: 933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot
245 12:02:01.202012 - {KERNEL_ADDR}: 0x01080000
246 12:02:01.202447 - {KERNEL}: 933881/tftp-deploy-25s6olht/kernel/uImage
247 12:02:01.202882 - {LAVA_MAC}: None
248 12:02:01.203363 - {PRESEED_CONFIG}: None
249 12:02:01.203798 - {PRESEED_LOCAL}: None
250 12:02:01.204263 - {RAMDISK_ADDR}: 0x08000000
251 12:02:01.204692 - {RAMDISK}: 933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot
252 12:02:01.205126 - {ROOT_PART}: None
253 12:02:01.205556 - {ROOT}: None
254 12:02:01.205983 - {SERVER_IP}: 192.168.6.2
255 12:02:01.206418 - {TEE_ADDR}: 0x83000000
256 12:02:01.206847 - {TEE}: None
257 12:02:01.207276 Parsed boot commands:
258 12:02:01.207692 - setenv autoload no
259 12:02:01.208147 - setenv initrd_high 0xffffffff
260 12:02:01.208577 - setenv fdt_high 0xffffffff
261 12:02:01.209004 - dhcp
262 12:02:01.209430 - setenv serverip 192.168.6.2
263 12:02:01.209854 - tftpboot 0x01080000 933881/tftp-deploy-25s6olht/kernel/uImage
264 12:02:01.210281 - tftpboot 0x08000000 933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot
265 12:02:01.210707 - tftpboot 0x01070000 933881/tftp-deploy-25s6olht/dtb/meson-g12b-a311d-libretech-cc.dtb
266 12:02:01.211128 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 12:02:01.211563 - bootm 0x01080000 0x08000000 0x01070000
268 12:02:01.212153 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 12:02:01.213808 start: 2.3 connect-device (timeout 00:05:00) [common]
271 12:02:01.214296 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 12:02:01.229536 Setting prompt string to ['lava-test: # ']
273 12:02:01.231187 end: 2.3 connect-device (duration 00:00:00) [common]
274 12:02:01.231837 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 12:02:01.232472 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 12:02:01.233049 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 12:02:01.234305 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 12:02:01.271199 >> OK - accepted request
279 12:02:01.273465 Returned 0 in 0 seconds
280 12:02:01.374614 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 12:02:01.376420 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 12:02:01.377030 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 12:02:01.377571 Setting prompt string to ['Hit any key to stop autoboot']
285 12:02:01.378062 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 12:02:01.379813 Trying 192.168.56.21...
287 12:02:01.380357 Connected to conserv1.
288 12:02:01.380814 Escape character is '^]'.
289 12:02:01.381268
290 12:02:01.381725 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 12:02:01.382186
292 12:02:13.457885 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 12:02:13.458529 bl2_stage_init 0x01
294 12:02:13.458960 bl2_stage_init 0x81
295 12:02:13.463653 hw id: 0x0000 - pwm id 0x01
296 12:02:13.464211 bl2_stage_init 0xc1
297 12:02:13.464633 bl2_stage_init 0x02
298 12:02:13.465060
299 12:02:13.469010 L0:00000000
300 12:02:13.469508 L1:20000703
301 12:02:13.469944 L2:00008067
302 12:02:13.470338 L3:14000000
303 12:02:13.474585 B2:00402000
304 12:02:13.475065 B1:e0f83180
305 12:02:13.475471
306 12:02:13.475866 TE: 58124
307 12:02:13.476297
308 12:02:13.480685 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 12:02:13.481148
310 12:02:13.481553 Board ID = 1
311 12:02:13.485807 Set A53 clk to 24M
312 12:02:13.486270 Set A73 clk to 24M
313 12:02:13.486673 Set clk81 to 24M
314 12:02:13.491426 A53 clk: 1200 MHz
315 12:02:13.491880 A73 clk: 1200 MHz
316 12:02:13.492303 CLK81: 166.6M
317 12:02:13.492697 smccc: 00012a91
318 12:02:13.496980 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 12:02:13.502585 board id: 1
320 12:02:13.508738 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 12:02:13.519115 fw parse done
322 12:02:13.525092 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 12:02:13.567763 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 12:02:13.578641 PIEI prepare done
325 12:02:13.579127 fastboot data load
326 12:02:13.579542 fastboot data verify
327 12:02:13.584263 verify result: 266
328 12:02:13.589857 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 12:02:13.590333 LPDDR4 probe
330 12:02:13.590738 ddr clk to 1584MHz
331 12:02:13.597861 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 12:02:13.635396
333 12:02:13.635932 dmc_version 0001
334 12:02:13.643349 Check phy result
335 12:02:13.647853 INFO : End of CA training
336 12:02:13.648369 INFO : End of initialization
337 12:02:13.653228 INFO : Training has run successfully!
338 12:02:13.653729 Check phy result
339 12:02:13.659199 INFO : End of initialization
340 12:02:13.659684 INFO : End of read enable training
341 12:02:13.664479 INFO : End of fine write leveling
342 12:02:13.670272 INFO : End of Write leveling coarse delay
343 12:02:13.670748 INFO : Training has run successfully!
344 12:02:13.671159 Check phy result
345 12:02:13.676037 INFO : End of initialization
346 12:02:13.676517 INFO : End of read dq deskew training
347 12:02:13.681445 INFO : End of MPR read delay center optimization
348 12:02:13.686979 INFO : End of write delay center optimization
349 12:02:13.692435 INFO : End of read delay center optimization
350 12:02:13.692911 INFO : End of max read latency training
351 12:02:13.698453 INFO : Training has run successfully!
352 12:02:13.698934 1D training succeed
353 12:02:13.707190 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 12:02:13.755151 Check phy result
355 12:02:13.756137 INFO : End of initialization
356 12:02:13.776611 INFO : End of 2D read delay Voltage center optimization
357 12:02:13.797993 INFO : End of 2D read delay Voltage center optimization
358 12:02:13.848826 INFO : End of 2D write delay Voltage center optimization
359 12:02:13.898173 INFO : End of 2D write delay Voltage center optimization
360 12:02:13.903803 INFO : Training has run successfully!
361 12:02:13.904292
362 12:02:13.904630 channel==0
363 12:02:13.909318 RxClkDly_Margin_A0==69 ps 7
364 12:02:13.909714 TxDqDly_Margin_A0==98 ps 10
365 12:02:13.915013 RxClkDly_Margin_A1==88 ps 9
366 12:02:13.915403 TxDqDly_Margin_A1==98 ps 10
367 12:02:13.915752 TrainedVREFDQ_A0==74
368 12:02:13.920514 TrainedVREFDQ_A1==74
369 12:02:13.920930 VrefDac_Margin_A0==25
370 12:02:13.921256 DeviceVref_Margin_A0==40
371 12:02:13.926112 VrefDac_Margin_A1==25
372 12:02:13.926501 DeviceVref_Margin_A1==40
373 12:02:13.926856
374 12:02:13.927200
375 12:02:13.931801 channel==1
376 12:02:13.932244 RxClkDly_Margin_A0==98 ps 10
377 12:02:13.932603 TxDqDly_Margin_A0==98 ps 10
378 12:02:13.938371 RxClkDly_Margin_A1==98 ps 10
379 12:02:13.938784 TxDqDly_Margin_A1==98 ps 10
380 12:02:13.943140 TrainedVREFDQ_A0==78
381 12:02:13.943532 TrainedVREFDQ_A1==77
382 12:02:13.943881 VrefDac_Margin_A0==23
383 12:02:13.948513 DeviceVref_Margin_A0==36
384 12:02:13.948901 VrefDac_Margin_A1==23
385 12:02:13.954071 DeviceVref_Margin_A1==37
386 12:02:13.954484
387 12:02:13.954816 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 12:02:13.959678
389 12:02:13.987833 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 12:02:13.988261 2D training succeed
391 12:02:13.993339 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 12:02:13.999221 auto size-- 65535DDR cs0 size: 2048MB
393 12:02:13.999628 DDR cs1 size: 2048MB
394 12:02:14.004649 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 12:02:14.005073 cs0 DataBus test pass
396 12:02:14.010416 cs1 DataBus test pass
397 12:02:14.010839 cs0 AddrBus test pass
398 12:02:14.011196 cs1 AddrBus test pass
399 12:02:14.011520
400 12:02:14.016146 100bdlr_step_size ps== 420
401 12:02:14.016545 result report
402 12:02:14.021296 boot times 0Enable ddr reg access
403 12:02:14.027714 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 12:02:14.041183 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 12:02:14.614115 0.0;M3 CHK:0;cm4_sp_mode 0
406 12:02:14.614632 MVN_1=0x00000000
407 12:02:14.619633 MVN_2=0x00000000
408 12:02:14.625372 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 12:02:14.625814 OPS=0x10
410 12:02:14.626115 ring efuse init
411 12:02:14.626406 chipver efuse init
412 12:02:14.633534 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 12:02:14.633937 [0.018961 Inits done]
414 12:02:14.641186 secure task start!
415 12:02:14.641651 high task start!
416 12:02:14.641958 low task start!
417 12:02:14.642280 run into bl31
418 12:02:14.647703 NOTICE: BL31: v1.3(release):4fc40b1
419 12:02:14.655780 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 12:02:14.656326 NOTICE: BL31: G12A normal boot!
421 12:02:14.681039 NOTICE: BL31: BL33 decompress pass
422 12:02:14.685573 ERROR: Error initializing runtime service opteed_fast
423 12:02:15.919530
424 12:02:15.919947
425 12:02:15.927855 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 12:02:15.928185
427 12:02:15.928394 Model: Libre Computer AML-A311D-CC Alta
428 12:02:16.136493 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 12:02:16.159805 DRAM: 2 GiB (effective 3.8 GiB)
430 12:02:16.302655 Core: 408 devices, 31 uclasses, devicetree: separate
431 12:02:16.308570 WDT: Not starting watchdog@f0d0
432 12:02:16.340881 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 12:02:16.353358 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 12:02:16.358431 ** Bad device specification mmc 0 **
435 12:02:16.368640 Card did not respond to voltage select! : -110
436 12:02:16.376274 ** Bad device specification mmc 0 **
437 12:02:16.376739 Couldn't find partition mmc 0
438 12:02:16.384517 Card did not respond to voltage select! : -110
439 12:02:16.390159 ** Bad device specification mmc 0 **
440 12:02:16.390616 Couldn't find partition mmc 0
441 12:02:16.395249 Error: could not access storage.
442 12:02:17.658528 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 12:02:17.659163 bl2_stage_init 0x01
444 12:02:17.659621 bl2_stage_init 0x81
445 12:02:17.664073 hw id: 0x0000 - pwm id 0x01
446 12:02:17.664554 bl2_stage_init 0xc1
447 12:02:17.664990 bl2_stage_init 0x02
448 12:02:17.665422
449 12:02:17.669658 L0:00000000
450 12:02:17.670118 L1:20000703
451 12:02:17.670550 L2:00008067
452 12:02:17.670977 L3:14000000
453 12:02:17.672465 B2:00402000
454 12:02:17.672919 B1:e0f83180
455 12:02:17.673344
456 12:02:17.673772 TE: 58159
457 12:02:17.674201
458 12:02:17.683572 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 12:02:17.684067
460 12:02:17.684502 Board ID = 1
461 12:02:17.684930 Set A53 clk to 24M
462 12:02:17.685354 Set A73 clk to 24M
463 12:02:17.689265 Set clk81 to 24M
464 12:02:17.689721 A53 clk: 1200 MHz
465 12:02:17.690151 A73 clk: 1200 MHz
466 12:02:17.694798 CLK81: 166.6M
467 12:02:17.695251 smccc: 00012ab5
468 12:02:17.700397 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 12:02:17.700853 board id: 1
470 12:02:17.705975 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 12:02:17.719706 fw parse done
472 12:02:17.724735 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 12:02:17.767477 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 12:02:17.779363 PIEI prepare done
475 12:02:17.779860 fastboot data load
476 12:02:17.780330 fastboot data verify
477 12:02:17.784923 verify result: 266
478 12:02:17.790447 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 12:02:17.790902 LPDDR4 probe
480 12:02:17.791333 ddr clk to 1584MHz
481 12:02:17.798463 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 12:02:17.835701
483 12:02:17.836206 dmc_version 0001
484 12:02:17.842413 Check phy result
485 12:02:17.848363 INFO : End of CA training
486 12:02:17.848824 INFO : End of initialization
487 12:02:17.853930 INFO : Training has run successfully!
488 12:02:17.854495 Check phy result
489 12:02:17.859554 INFO : End of initialization
490 12:02:17.860088 INFO : End of read enable training
491 12:02:17.865120 INFO : End of fine write leveling
492 12:02:17.870695 INFO : End of Write leveling coarse delay
493 12:02:17.871190 INFO : Training has run successfully!
494 12:02:17.871626 Check phy result
495 12:02:17.876325 INFO : End of initialization
496 12:02:17.876825 INFO : End of read dq deskew training
497 12:02:17.881920 INFO : End of MPR read delay center optimization
498 12:02:17.887562 INFO : End of write delay center optimization
499 12:02:17.893108 INFO : End of read delay center optimization
500 12:02:17.893599 INFO : End of max read latency training
501 12:02:17.898709 INFO : Training has run successfully!
502 12:02:17.899203 1D training succeed
503 12:02:17.907833 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 12:02:17.955551 Check phy result
505 12:02:17.956097 INFO : End of initialization
506 12:02:17.977986 INFO : End of 2D read delay Voltage center optimization
507 12:02:17.998077 INFO : End of 2D read delay Voltage center optimization
508 12:02:18.049980 INFO : End of 2D write delay Voltage center optimization
509 12:02:18.099279 INFO : End of 2D write delay Voltage center optimization
510 12:02:18.104785 INFO : Training has run successfully!
511 12:02:18.105321
512 12:02:18.105756 channel==0
513 12:02:18.110531 RxClkDly_Margin_A0==88 ps 9
514 12:02:18.111046 TxDqDly_Margin_A0==98 ps 10
515 12:02:18.115962 RxClkDly_Margin_A1==88 ps 9
516 12:02:18.116522 TxDqDly_Margin_A1==98 ps 10
517 12:02:18.116961 TrainedVREFDQ_A0==74
518 12:02:18.121574 TrainedVREFDQ_A1==74
519 12:02:18.122106 VrefDac_Margin_A0==25
520 12:02:18.122539 DeviceVref_Margin_A0==40
521 12:02:18.127195 VrefDac_Margin_A1==25
522 12:02:18.127710 DeviceVref_Margin_A1==40
523 12:02:18.128182
524 12:02:18.128614
525 12:02:18.132792 channel==1
526 12:02:18.133311 RxClkDly_Margin_A0==98 ps 10
527 12:02:18.133750 TxDqDly_Margin_A0==98 ps 10
528 12:02:18.138452 RxClkDly_Margin_A1==98 ps 10
529 12:02:18.138971 TxDqDly_Margin_A1==98 ps 10
530 12:02:18.143957 TrainedVREFDQ_A0==77
531 12:02:18.144509 TrainedVREFDQ_A1==78
532 12:02:18.144947 VrefDac_Margin_A0==22
533 12:02:18.149568 DeviceVref_Margin_A0==37
534 12:02:18.150083 VrefDac_Margin_A1==22
535 12:02:18.155193 DeviceVref_Margin_A1==36
536 12:02:18.155703
537 12:02:18.156174 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 12:02:18.160760
539 12:02:18.188744 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 12:02:18.189316 2D training succeed
541 12:02:18.194460 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 12:02:18.200030 auto size-- 65535DDR cs0 size: 2048MB
543 12:02:18.200573 DDR cs1 size: 2048MB
544 12:02:18.205591 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 12:02:18.206123 cs0 DataBus test pass
546 12:02:18.211169 cs1 DataBus test pass
547 12:02:18.211687 cs0 AddrBus test pass
548 12:02:18.212156 cs1 AddrBus test pass
549 12:02:18.212589
550 12:02:18.216762 100bdlr_step_size ps== 420
551 12:02:18.217298 result report
552 12:02:18.222435 boot times 0Enable ddr reg access
553 12:02:18.227869 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 12:02:18.241376 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 12:02:18.813336 0.0;M3 CHK:0;cm4_sp_mode 0
556 12:02:18.813959 MVN_1=0x00000000
557 12:02:18.818820 MVN_2=0x00000000
558 12:02:18.824554 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 12:02:18.825058 OPS=0x10
560 12:02:18.825503 ring efuse init
561 12:02:18.825935 chipver efuse init
562 12:02:18.830110 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 12:02:18.835699 [0.018961 Inits done]
564 12:02:18.836234 secure task start!
565 12:02:18.836666 high task start!
566 12:02:18.840276 low task start!
567 12:02:18.840786 run into bl31
568 12:02:18.846972 NOTICE: BL31: v1.3(release):4fc40b1
569 12:02:18.854780 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 12:02:18.855285 NOTICE: BL31: G12A normal boot!
571 12:02:18.880129 NOTICE: BL31: BL33 decompress pass
572 12:02:18.885790 ERROR: Error initializing runtime service opteed_fast
573 12:02:20.118659
574 12:02:20.119279
575 12:02:20.127036 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 12:02:20.127553
577 12:02:20.128025 Model: Libre Computer AML-A311D-CC Alta
578 12:02:20.335515 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 12:02:20.358849 DRAM: 2 GiB (effective 3.8 GiB)
580 12:02:20.501919 Core: 408 devices, 31 uclasses, devicetree: separate
581 12:02:20.507793 WDT: Not starting watchdog@f0d0
582 12:02:20.540051 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 12:02:20.552461 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 12:02:20.557471 ** Bad device specification mmc 0 **
585 12:02:20.567784 Card did not respond to voltage select! : -110
586 12:02:20.575455 ** Bad device specification mmc 0 **
587 12:02:20.575968 Couldn't find partition mmc 0
588 12:02:20.583789 Card did not respond to voltage select! : -110
589 12:02:20.589302 ** Bad device specification mmc 0 **
590 12:02:20.589801 Couldn't find partition mmc 0
591 12:02:20.594349 Error: could not access storage.
592 12:02:20.937873 Net: eth0: ethernet@ff3f0000
593 12:02:20.938452 starting USB...
594 12:02:21.189678 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 12:02:21.190307 Starting the controller
596 12:02:21.196656 USB XHCI 1.10
597 12:02:22.907055 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 12:02:22.907584 bl2_stage_init 0x01
599 12:02:22.907973 bl2_stage_init 0x81
600 12:02:22.912495 hw id: 0x0000 - pwm id 0x01
601 12:02:22.912817 bl2_stage_init 0xc1
602 12:02:22.913080 bl2_stage_init 0x02
603 12:02:22.913338
604 12:02:22.918148 L0:00000000
605 12:02:22.918541 L1:20000703
606 12:02:22.918877 L2:00008067
607 12:02:22.919248 L3:14000000
608 12:02:22.923743 B2:00402000
609 12:02:22.924192 B1:e0f83180
610 12:02:22.924530
611 12:02:22.924906 TE: 58124
612 12:02:22.925243
613 12:02:22.929342 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 12:02:22.929736
615 12:02:22.930040 Board ID = 1
616 12:02:22.935031 Set A53 clk to 24M
617 12:02:22.935427 Set A73 clk to 24M
618 12:02:22.935807 Set clk81 to 24M
619 12:02:22.940727 A53 clk: 1200 MHz
620 12:02:22.941132 A73 clk: 1200 MHz
621 12:02:22.941466 CLK81: 166.6M
622 12:02:22.941834 smccc: 00012a92
623 12:02:22.946153 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 12:02:22.951761 board id: 1
625 12:02:22.957588 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 12:02:22.968201 fw parse done
627 12:02:22.974170 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 12:02:23.016804 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 12:02:23.027713 PIEI prepare done
630 12:02:23.028109 fastboot data load
631 12:02:23.028383 fastboot data verify
632 12:02:23.033329 verify result: 266
633 12:02:23.039006 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 12:02:23.039322 LPDDR4 probe
635 12:02:23.039579 ddr clk to 1584MHz
636 12:02:23.046963 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 12:02:23.084214
638 12:02:23.084592 dmc_version 0001
639 12:02:23.090926 Check phy result
640 12:02:23.096791 INFO : End of CA training
641 12:02:23.097192 INFO : End of initialization
642 12:02:23.102378 INFO : Training has run successfully!
643 12:02:23.102692 Check phy result
644 12:02:23.108014 INFO : End of initialization
645 12:02:23.108333 INFO : End of read enable training
646 12:02:23.113612 INFO : End of fine write leveling
647 12:02:23.119178 INFO : End of Write leveling coarse delay
648 12:02:23.119581 INFO : Training has run successfully!
649 12:02:23.119881 Check phy result
650 12:02:23.124831 INFO : End of initialization
651 12:02:23.125229 INFO : End of read dq deskew training
652 12:02:23.130447 INFO : End of MPR read delay center optimization
653 12:02:23.136007 INFO : End of write delay center optimization
654 12:02:23.141559 INFO : End of read delay center optimization
655 12:02:23.141951 INFO : End of max read latency training
656 12:02:23.147260 INFO : Training has run successfully!
657 12:02:23.147657 1D training succeed
658 12:02:23.156399 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 12:02:23.203933 Check phy result
660 12:02:23.204577 INFO : End of initialization
661 12:02:23.225746 INFO : End of 2D read delay Voltage center optimization
662 12:02:23.245993 INFO : End of 2D read delay Voltage center optimization
663 12:02:23.298059 INFO : End of 2D write delay Voltage center optimization
664 12:02:23.347459 INFO : End of 2D write delay Voltage center optimization
665 12:02:23.353101 INFO : Training has run successfully!
666 12:02:23.353498
667 12:02:23.353842 channel==0
668 12:02:23.358577 RxClkDly_Margin_A0==88 ps 9
669 12:02:23.358883 TxDqDly_Margin_A0==98 ps 10
670 12:02:23.361868 RxClkDly_Margin_A1==88 ps 9
671 12:02:23.362257 TxDqDly_Margin_A1==88 ps 9
672 12:02:23.367496 TrainedVREFDQ_A0==74
673 12:02:23.367881 TrainedVREFDQ_A1==74
674 12:02:23.368254 VrefDac_Margin_A0==25
675 12:02:23.373102 DeviceVref_Margin_A0==40
676 12:02:23.373471 VrefDac_Margin_A1==25
677 12:02:23.378663 DeviceVref_Margin_A1==40
678 12:02:23.379030
679 12:02:23.379336
680 12:02:23.379660 channel==1
681 12:02:23.379949 RxClkDly_Margin_A0==98 ps 10
682 12:02:23.384299 TxDqDly_Margin_A0==98 ps 10
683 12:02:23.384660 RxClkDly_Margin_A1==88 ps 9
684 12:02:23.389961 TxDqDly_Margin_A1==98 ps 10
685 12:02:23.390334 TrainedVREFDQ_A0==77
686 12:02:23.390634 TrainedVREFDQ_A1==77
687 12:02:23.395518 VrefDac_Margin_A0==22
688 12:02:23.395888 DeviceVref_Margin_A0==37
689 12:02:23.401079 VrefDac_Margin_A1==24
690 12:02:23.401414 DeviceVref_Margin_A1==37
691 12:02:23.401742
692 12:02:23.406633 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 12:02:23.407008
694 12:02:23.434604 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 12:02:23.440240 2D training succeed
696 12:02:23.445817 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 12:02:23.446195 auto size-- 65535DDR cs0 size: 2048MB
698 12:02:23.451438 DDR cs1 size: 2048MB
699 12:02:23.451814 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 12:02:23.457049 cs0 DataBus test pass
701 12:02:23.457418 cs1 DataBus test pass
702 12:02:23.457749 cs0 AddrBus test pass
703 12:02:23.462631 cs1 AddrBus test pass
704 12:02:23.462999
705 12:02:23.463297 100bdlr_step_size ps== 420
706 12:02:23.463620 result report
707 12:02:23.468251 boot times 0Enable ddr reg access
708 12:02:23.475877 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 12:02:23.489383 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 12:02:24.063100 0.0;M3 CHK:0;cm4_sp_mode 0
711 12:02:24.063753 MVN_1=0x00000000
712 12:02:24.068578 MVN_2=0x00000000
713 12:02:24.074270 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 12:02:24.074746 OPS=0x10
715 12:02:24.075183 ring efuse init
716 12:02:24.075611 chipver efuse init
717 12:02:24.082563 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 12:02:24.083059 [0.018960 Inits done]
719 12:02:24.083488 secure task start!
720 12:02:24.090110 high task start!
721 12:02:24.090576 low task start!
722 12:02:24.091003 run into bl31
723 12:02:24.096819 NOTICE: BL31: v1.3(release):4fc40b1
724 12:02:24.104689 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 12:02:24.105157 NOTICE: BL31: G12A normal boot!
726 12:02:24.129842 NOTICE: BL31: BL33 decompress pass
727 12:02:24.135632 ERROR: Error initializing runtime service opteed_fast
728 12:02:25.368630
729 12:02:25.369234
730 12:02:25.377041 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 12:02:25.377530
732 12:02:25.377968 Model: Libre Computer AML-A311D-CC Alta
733 12:02:25.584595 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 12:02:25.608825 DRAM: 2 GiB (effective 3.8 GiB)
735 12:02:25.751821 Core: 408 devices, 31 uclasses, devicetree: separate
736 12:02:25.757719 WDT: Not starting watchdog@f0d0
737 12:02:25.789892 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 12:02:25.802577 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 12:02:25.807432 ** Bad device specification mmc 0 **
740 12:02:25.817804 Card did not respond to voltage select! : -110
741 12:02:25.825385 ** Bad device specification mmc 0 **
742 12:02:25.825884 Couldn't find partition mmc 0
743 12:02:25.833717 Card did not respond to voltage select! : -110
744 12:02:25.839225 ** Bad device specification mmc 0 **
745 12:02:25.839698 Couldn't find partition mmc 0
746 12:02:25.844332 Error: could not access storage.
747 12:02:26.186759 Net: eth0: ethernet@ff3f0000
748 12:02:26.187389 starting USB...
749 12:02:26.438594 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 12:02:26.439201 Starting the controller
751 12:02:26.445661 USB XHCI 1.10
752 12:02:28.607244 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 12:02:28.608223 bl2_stage_init 0x01
754 12:02:28.608583 bl2_stage_init 0x81
755 12:02:28.612887 hw id: 0x0000 - pwm id 0x01
756 12:02:28.613476 bl2_stage_init 0xc1
757 12:02:28.613995 bl2_stage_init 0x02
758 12:02:28.614277
759 12:02:28.618545 L0:00000000
760 12:02:28.619063 L1:20000703
761 12:02:28.619466 L2:00008067
762 12:02:28.619860 L3:14000000
763 12:02:28.624093 B2:00402000
764 12:02:28.624568 B1:e0f83180
765 12:02:28.624966
766 12:02:28.625362 TE: 58167
767 12:02:28.625756
768 12:02:28.629701 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 12:02:28.630186
770 12:02:28.630587 Board ID = 1
771 12:02:28.635222 Set A53 clk to 24M
772 12:02:28.635704 Set A73 clk to 24M
773 12:02:28.636130 Set clk81 to 24M
774 12:02:28.640816 A53 clk: 1200 MHz
775 12:02:28.641295 A73 clk: 1200 MHz
776 12:02:28.641687 CLK81: 166.6M
777 12:02:28.642074 smccc: 00012abd
778 12:02:28.646628 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 12:02:28.652121 board id: 1
780 12:02:28.658011 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 12:02:28.668442 fw parse done
782 12:02:28.674435 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 12:02:28.717038 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 12:02:28.728036 PIEI prepare done
785 12:02:28.728553 fastboot data load
786 12:02:28.728958 fastboot data verify
787 12:02:28.733642 verify result: 266
788 12:02:28.739235 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 12:02:28.739730 LPDDR4 probe
790 12:02:28.740172 ddr clk to 1584MHz
791 12:02:28.747216 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 12:02:28.784489
793 12:02:28.785016 dmc_version 0001
794 12:02:28.791244 Check phy result
795 12:02:28.797089 INFO : End of CA training
796 12:02:28.797587 INFO : End of initialization
797 12:02:28.802591 INFO : Training has run successfully!
798 12:02:28.803090 Check phy result
799 12:02:28.808293 INFO : End of initialization
800 12:02:28.808798 INFO : End of read enable training
801 12:02:28.811575 INFO : End of fine write leveling
802 12:02:28.817094 INFO : End of Write leveling coarse delay
803 12:02:28.822700 INFO : Training has run successfully!
804 12:02:28.823195 Check phy result
805 12:02:28.823590 INFO : End of initialization
806 12:02:28.828341 INFO : End of read dq deskew training
807 12:02:28.833911 INFO : End of MPR read delay center optimization
808 12:02:28.834412 INFO : End of write delay center optimization
809 12:02:28.839499 INFO : End of read delay center optimization
810 12:02:28.845120 INFO : End of max read latency training
811 12:02:28.845622 INFO : Training has run successfully!
812 12:02:28.850628 1D training succeed
813 12:02:28.856659 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 12:02:28.904206 Check phy result
815 12:02:28.904732 INFO : End of initialization
816 12:02:28.925895 INFO : End of 2D read delay Voltage center optimization
817 12:02:28.946156 INFO : End of 2D read delay Voltage center optimization
818 12:02:28.998147 INFO : End of 2D write delay Voltage center optimization
819 12:02:29.047579 INFO : End of 2D write delay Voltage center optimization
820 12:02:29.053108 INFO : Training has run successfully!
821 12:02:29.053612
822 12:02:29.054013 channel==0
823 12:02:29.058743 RxClkDly_Margin_A0==78 ps 8
824 12:02:29.059256 TxDqDly_Margin_A0==98 ps 10
825 12:02:29.064309 RxClkDly_Margin_A1==88 ps 9
826 12:02:29.064806 TxDqDly_Margin_A1==98 ps 10
827 12:02:29.065201 TrainedVREFDQ_A0==74
828 12:02:29.069942 TrainedVREFDQ_A1==76
829 12:02:29.070432 VrefDac_Margin_A0==25
830 12:02:29.070823 DeviceVref_Margin_A0==40
831 12:02:29.075480 VrefDac_Margin_A1==25
832 12:02:29.075961 DeviceVref_Margin_A1==38
833 12:02:29.076382
834 12:02:29.076766
835 12:02:29.081098 channel==1
836 12:02:29.081598 RxClkDly_Margin_A0==98 ps 10
837 12:02:29.081988 TxDqDly_Margin_A0==98 ps 10
838 12:02:29.086702 RxClkDly_Margin_A1==98 ps 10
839 12:02:29.087188 TxDqDly_Margin_A1==98 ps 10
840 12:02:29.092321 TrainedVREFDQ_A0==77
841 12:02:29.092810 TrainedVREFDQ_A1==78
842 12:02:29.093202 VrefDac_Margin_A0==22
843 12:02:29.097946 DeviceVref_Margin_A0==37
844 12:02:29.098434 VrefDac_Margin_A1==23
845 12:02:29.103500 DeviceVref_Margin_A1==36
846 12:02:29.104012
847 12:02:29.104432 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 12:02:29.109131
849 12:02:29.137062 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 12:02:29.137615 2D training succeed
851 12:02:29.142729 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 12:02:29.148313 auto size-- 65535DDR cs0 size: 2048MB
853 12:02:29.148810 DDR cs1 size: 2048MB
854 12:02:29.153929 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 12:02:29.154416 cs0 DataBus test pass
856 12:02:29.159503 cs1 DataBus test pass
857 12:02:29.160019 cs0 AddrBus test pass
858 12:02:29.160420 cs1 AddrBus test pass
859 12:02:29.160805
860 12:02:29.165099 100bdlr_step_size ps== 420
861 12:02:29.165597 result report
862 12:02:29.170716 boot times 0Enable ddr reg access
863 12:02:29.176289 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 12:02:29.189684 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 12:02:29.763337 0.0;M3 CHK:0;cm4_sp_mode 0
866 12:02:29.763922 MVN_1=0x00000000
867 12:02:29.768877 MVN_2=0x00000000
868 12:02:29.774629 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 12:02:29.775129 OPS=0x10
870 12:02:29.775527 ring efuse init
871 12:02:29.775911 chipver efuse init
872 12:02:29.780256 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 12:02:29.785860 [0.018961 Inits done]
874 12:02:29.786348 secure task start!
875 12:02:29.786746 high task start!
876 12:02:29.790453 low task start!
877 12:02:29.790940 run into bl31
878 12:02:29.797097 NOTICE: BL31: v1.3(release):4fc40b1
879 12:02:29.804908 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 12:02:29.805415 NOTICE: BL31: G12A normal boot!
881 12:02:29.830320 NOTICE: BL31: BL33 decompress pass
882 12:02:29.836060 ERROR: Error initializing runtime service opteed_fast
883 12:02:31.068968
884 12:02:31.069602
885 12:02:31.077348 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 12:02:31.077862
887 12:02:31.078281 Model: Libre Computer AML-A311D-CC Alta
888 12:02:31.285716 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 12:02:31.309096 DRAM: 2 GiB (effective 3.8 GiB)
890 12:02:31.452104 Core: 408 devices, 31 uclasses, devicetree: separate
891 12:02:31.457963 WDT: Not starting watchdog@f0d0
892 12:02:31.490223 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 12:02:31.502643 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 12:02:31.507662 ** Bad device specification mmc 0 **
895 12:02:31.517989 Card did not respond to voltage select! : -110
896 12:02:31.525642 ** Bad device specification mmc 0 **
897 12:02:31.526102 Couldn't find partition mmc 0
898 12:02:31.533968 Card did not respond to voltage select! : -110
899 12:02:31.539505 ** Bad device specification mmc 0 **
900 12:02:31.539966 Couldn't find partition mmc 0
901 12:02:31.544564 Error: could not access storage.
902 12:02:31.887012 Net: eth0: ethernet@ff3f0000
903 12:02:31.887555 starting USB...
904 12:02:32.138872 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 12:02:32.139409 Starting the controller
906 12:02:32.145805 USB XHCI 1.10
907 12:02:33.699783 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 12:02:33.708159 scanning usb for storage devices... 0 Storage Device(s) found
910 12:02:33.759627 Hit any key to stop autoboot: 1
911 12:02:33.760651 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 12:02:33.761269 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
913 12:02:33.761742 Setting prompt string to ['=>']
914 12:02:33.762219 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
915 12:02:33.775610 0
916 12:02:33.776510 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 12:02:33.777002 Sending with 10 millisecond of delay
919 12:02:34.911490 => setenv autoload no
920 12:02:34.922290 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
921 12:02:34.927147 setenv autoload no
922 12:02:34.927853 Sending with 10 millisecond of delay
924 12:02:36.725178 => setenv initrd_high 0xffffffff
925 12:02:36.736295 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
926 12:02:36.737214 setenv initrd_high 0xffffffff
927 12:02:36.737925 Sending with 10 millisecond of delay
929 12:02:38.355775 => setenv fdt_high 0xffffffff
930 12:02:38.366417 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 12:02:38.367018 setenv fdt_high 0xffffffff
932 12:02:38.367513 Sending with 10 millisecond of delay
934 12:02:38.659070 => dhcp
935 12:02:38.669639 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 12:02:38.670179 dhcp
937 12:02:38.670424 Speed: 1000, full duplex
938 12:02:38.670631 BOOTP broadcast 1
939 12:02:38.678471 DHCP client bound to address 192.168.6.27 (9 ms)
940 12:02:38.678974 Sending with 10 millisecond of delay
942 12:02:40.355365 => setenv serverip 192.168.6.2
943 12:02:40.366191 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 12:02:40.367044 setenv serverip 192.168.6.2
945 12:02:40.367719 Sending with 10 millisecond of delay
947 12:02:44.092703 => tftpboot 0x01080000 933881/tftp-deploy-25s6olht/kernel/uImage
948 12:02:44.103524 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 12:02:44.104227 tftpboot 0x01080000 933881/tftp-deploy-25s6olht/kernel/uImage
950 12:02:44.104571 Speed: 1000, full duplex
951 12:02:44.104853 Using ethernet@ff3f0000 device
952 12:02:44.106115 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 12:02:44.113216 Filename '933881/tftp-deploy-25s6olht/kernel/uImage'.
954 12:02:44.115575 Load address: 0x1080000
955 12:02:47.064020 Loading: *################################################## 43.6 MiB
956 12:02:47.064647 14.8 MiB/s
957 12:02:47.065067 done
958 12:02:47.068466 Bytes transferred = 45713984 (2b98a40 hex)
959 12:02:47.069270 Sending with 10 millisecond of delay
961 12:02:51.761938 => tftpboot 0x08000000 933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot
962 12:02:51.772649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
963 12:02:51.773168 tftpboot 0x08000000 933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot
964 12:02:51.773404 Speed: 1000, full duplex
965 12:02:51.773610 Using ethernet@ff3f0000 device
966 12:02:51.775214 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 12:02:51.783837 Filename '933881/tftp-deploy-25s6olht/ramdisk/ramdisk.cpio.gz.uboot'.
968 12:02:51.784194 Load address: 0x8000000
969 12:02:59.029392 Loading: *#############T #################################### UDP wrong checksum 00000005 000080f4
970 12:03:04.029569 T UDP wrong checksum 00000005 000080f4
971 12:03:14.032880 T T UDP wrong checksum 00000005 000080f4
972 12:03:34.036797 T T T T UDP wrong checksum 00000005 000080f4
973 12:03:39.194974 T UDP wrong checksum 000000ff 00006ddb
974 12:03:39.234479 UDP wrong checksum 000000ff 000000ce
975 12:03:49.041154 T
976 12:03:49.041965 Retry count exceeded; starting again
978 12:03:49.043716 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
981 12:03:49.046097 end: 2.4 uboot-commands (duration 00:01:48) [common]
983 12:03:49.047822 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
985 12:03:49.049221 end: 2 uboot-action (duration 00:01:48) [common]
987 12:03:49.051245 Cleaning after the job
988 12:03:49.051971 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/ramdisk
989 12:03:49.053746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/kernel
990 12:03:49.100982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/dtb
991 12:03:49.101966 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933881/tftp-deploy-25s6olht/modules
992 12:03:49.124010 start: 4.1 power-off (timeout 00:00:30) [common]
993 12:03:49.124813 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
994 12:03:49.158399 >> OK - accepted request
995 12:03:49.160609 Returned 0 in 0 seconds
996 12:03:49.261549 end: 4.1 power-off (duration 00:00:00) [common]
998 12:03:49.262787 start: 4.2 read-feedback (timeout 00:10:00) [common]
999 12:03:49.263577 Listened to connection for namespace 'common' for up to 1s
1000 12:03:50.264312 Finalising connection for namespace 'common'
1001 12:03:50.265261 Disconnecting from shell: Finalise
1002 12:03:50.265968 =>
1003 12:03:50.367271 end: 4.2 read-feedback (duration 00:00:01) [common]
1004 12:03:50.368273 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933881
1005 12:03:50.703570 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933881
1006 12:03:50.704323 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.