Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 12:39:17.582089 lava-dispatcher, installed at version: 2024.01
2 12:39:17.582934 start: 0 validate
3 12:39:17.583417 Start time: 2024-11-04 12:39:17.583387+00:00 (UTC)
4 12:39:17.583942 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:39:17.584523 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 12:39:17.626014 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:39:17.626559 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fulfh%2Fnext%2Fmmc-v6.12-rc3-75-g84185573da38%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 12:39:17.656599 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:39:17.657205 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fulfh%2Fnext%2Fmmc-v6.12-rc3-75-g84185573da38%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 12:39:17.688228 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:39:17.688716 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fulfh%2Fnext%2Fmmc-v6.12-rc3-75-g84185573da38%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 12:39:17.725362 validate duration: 0.14
14 12:39:17.726224 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:39:17.726578 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:39:17.726894 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:39:17.727484 Not decompressing ramdisk as can be used compressed.
18 12:39:17.727935 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 12:39:17.728220 saving as /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/ramdisk/rootfs.cpio.gz
20 12:39:17.728494 total size: 47897469 (45 MB)
21 12:39:17.768099 progress 0 % (0 MB)
22 12:39:17.806143 progress 5 % (2 MB)
23 12:39:17.836512 progress 10 % (4 MB)
24 12:39:17.866516 progress 15 % (6 MB)
25 12:39:17.896907 progress 20 % (9 MB)
26 12:39:17.926972 progress 25 % (11 MB)
27 12:39:17.957082 progress 30 % (13 MB)
28 12:39:17.986976 progress 35 % (16 MB)
29 12:39:18.016818 progress 40 % (18 MB)
30 12:39:18.047146 progress 45 % (20 MB)
31 12:39:18.077029 progress 50 % (22 MB)
32 12:39:18.106877 progress 55 % (25 MB)
33 12:39:18.137266 progress 60 % (27 MB)
34 12:39:18.167541 progress 65 % (29 MB)
35 12:39:18.197529 progress 70 % (32 MB)
36 12:39:18.227249 progress 75 % (34 MB)
37 12:39:18.257481 progress 80 % (36 MB)
38 12:39:18.287371 progress 85 % (38 MB)
39 12:39:18.317133 progress 90 % (41 MB)
40 12:39:18.349347 progress 95 % (43 MB)
41 12:39:18.378783 progress 100 % (45 MB)
42 12:39:18.379509 45 MB downloaded in 0.65 s (70.17 MB/s)
43 12:39:18.380097 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:39:18.381005 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:39:18.381295 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:39:18.381568 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:39:18.382040 downloading http://storage.kernelci.org/ulfh/next/mmc-v6.12-rc3-75-g84185573da38/arm64/defconfig/gcc-12/kernel/Image
49 12:39:18.382291 saving as /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/kernel/Image
50 12:39:18.382501 total size: 45713920 (43 MB)
51 12:39:18.382711 No compression specified
52 12:39:18.419621 progress 0 % (0 MB)
53 12:39:18.447299 progress 5 % (2 MB)
54 12:39:18.475537 progress 10 % (4 MB)
55 12:39:18.503466 progress 15 % (6 MB)
56 12:39:18.531301 progress 20 % (8 MB)
57 12:39:18.558798 progress 25 % (10 MB)
58 12:39:18.586972 progress 30 % (13 MB)
59 12:39:18.614772 progress 35 % (15 MB)
60 12:39:18.642531 progress 40 % (17 MB)
61 12:39:18.670391 progress 45 % (19 MB)
62 12:39:18.698198 progress 50 % (21 MB)
63 12:39:18.726173 progress 55 % (24 MB)
64 12:39:18.753977 progress 60 % (26 MB)
65 12:39:18.781880 progress 65 % (28 MB)
66 12:39:18.809758 progress 70 % (30 MB)
67 12:39:18.837675 progress 75 % (32 MB)
68 12:39:18.865616 progress 80 % (34 MB)
69 12:39:18.893481 progress 85 % (37 MB)
70 12:39:18.921608 progress 90 % (39 MB)
71 12:39:18.949692 progress 95 % (41 MB)
72 12:39:18.977516 progress 100 % (43 MB)
73 12:39:18.978050 43 MB downloaded in 0.60 s (73.20 MB/s)
74 12:39:18.978538 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:39:18.979358 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:39:18.979634 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:39:18.979900 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:39:18.980394 downloading http://storage.kernelci.org/ulfh/next/mmc-v6.12-rc3-75-g84185573da38/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 12:39:18.980674 saving as /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/dtb/meson-g12b-a311d-libretech-cc.dtb
81 12:39:18.980885 total size: 54703 (0 MB)
82 12:39:18.981095 No compression specified
83 12:39:19.018495 progress 59 % (0 MB)
84 12:39:19.019356 progress 100 % (0 MB)
85 12:39:19.019915 0 MB downloaded in 0.04 s (1.34 MB/s)
86 12:39:19.020454 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:39:19.021275 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:39:19.021536 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:39:19.021798 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:39:19.022244 downloading http://storage.kernelci.org/ulfh/next/mmc-v6.12-rc3-75-g84185573da38/arm64/defconfig/gcc-12/modules.tar.xz
92 12:39:19.022493 saving as /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/modules/modules.tar
93 12:39:19.022698 total size: 11606276 (11 MB)
94 12:39:19.022908 Using unxz to decompress xz
95 12:39:19.057293 progress 0 % (0 MB)
96 12:39:19.122782 progress 5 % (0 MB)
97 12:39:19.196409 progress 10 % (1 MB)
98 12:39:19.292254 progress 15 % (1 MB)
99 12:39:19.383690 progress 20 % (2 MB)
100 12:39:19.461969 progress 25 % (2 MB)
101 12:39:19.538098 progress 30 % (3 MB)
102 12:39:19.613517 progress 35 % (3 MB)
103 12:39:19.690395 progress 40 % (4 MB)
104 12:39:19.765457 progress 45 % (5 MB)
105 12:39:19.848534 progress 50 % (5 MB)
106 12:39:19.924611 progress 55 % (6 MB)
107 12:39:20.008610 progress 60 % (6 MB)
108 12:39:20.088226 progress 65 % (7 MB)
109 12:39:20.163793 progress 70 % (7 MB)
110 12:39:20.245463 progress 75 % (8 MB)
111 12:39:20.327930 progress 80 % (8 MB)
112 12:39:20.406844 progress 85 % (9 MB)
113 12:39:20.484526 progress 90 % (9 MB)
114 12:39:20.561228 progress 95 % (10 MB)
115 12:39:20.637595 progress 100 % (11 MB)
116 12:39:20.648356 11 MB downloaded in 1.63 s (6.81 MB/s)
117 12:39:20.648921 end: 1.4.1 http-download (duration 00:00:02) [common]
119 12:39:20.649749 end: 1.4 download-retry (duration 00:00:02) [common]
120 12:39:20.650018 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 12:39:20.650284 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 12:39:20.650532 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:39:20.650785 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 12:39:20.651371 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn
125 12:39:20.651835 makedir: /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin
126 12:39:20.652481 makedir: /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/tests
127 12:39:20.653187 makedir: /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/results
128 12:39:20.653863 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-add-keys
129 12:39:20.654893 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-add-sources
130 12:39:20.655894 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-background-process-start
131 12:39:20.656966 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-background-process-stop
132 12:39:20.658071 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-common-functions
133 12:39:20.659066 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-echo-ipv4
134 12:39:20.660068 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-install-packages
135 12:39:20.661050 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-installed-packages
136 12:39:20.662035 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-os-build
137 12:39:20.663004 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-probe-channel
138 12:39:20.663963 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-probe-ip
139 12:39:20.665005 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-target-ip
140 12:39:20.665968 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-target-mac
141 12:39:20.666931 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-target-storage
142 12:39:20.667900 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-case
143 12:39:20.668921 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-event
144 12:39:20.669878 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-feedback
145 12:39:20.670834 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-raise
146 12:39:20.671782 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-reference
147 12:39:20.672795 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-runner
148 12:39:20.673763 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-set
149 12:39:20.674716 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-test-shell
150 12:39:20.675674 Updating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-install-packages (oe)
151 12:39:20.676869 Updating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/bin/lava-installed-packages (oe)
152 12:39:20.677793 Creating /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/environment
153 12:39:20.678560 LAVA metadata
154 12:39:20.679097 - LAVA_JOB_ID=933942
155 12:39:20.679572 - LAVA_DISPATCHER_IP=192.168.6.2
156 12:39:20.680315 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 12:39:20.682225 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 12:39:20.682874 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 12:39:20.683325 skipped lava-vland-overlay
160 12:39:20.683855 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 12:39:20.684516 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 12:39:20.684952 skipped lava-multinode-overlay
163 12:39:20.685458 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 12:39:20.685959 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 12:39:20.686428 Loading test definitions
166 12:39:20.686969 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 12:39:20.687401 Using /lava-933942 at stage 0
168 12:39:20.689497 uuid=933942_1.5.2.4.1 testdef=None
169 12:39:20.690064 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 12:39:20.690575 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 12:39:20.692988 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 12:39:20.693838 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 12:39:20.695964 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 12:39:20.696870 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 12:39:20.698933 runner path: /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/0/tests/0_igt-gpu-panfrost test_uuid 933942_1.5.2.4.1
178 12:39:20.699489 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 12:39:20.700340 Creating lava-test-runner.conf files
181 12:39:20.700550 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933942/lava-overlay-he6kfrmn/lava-933942/0 for stage 0
182 12:39:20.700888 - 0_igt-gpu-panfrost
183 12:39:20.701235 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 12:39:20.701515 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 12:39:20.724718 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 12:39:20.725102 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 12:39:20.725368 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 12:39:20.725633 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 12:39:20.725895 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 12:39:28.223369 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 12:39:28.223834 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 12:39:28.224233 extracting modules file /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk
193 12:39:29.634915 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 12:39:29.635366 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 12:39:29.635640 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933942/compress-overlay-kpbnqt1f/overlay-1.5.2.5.tar.gz to ramdisk
196 12:39:29.635854 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933942/compress-overlay-kpbnqt1f/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk
197 12:39:29.665474 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 12:39:29.665832 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 12:39:29.666099 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 12:39:29.666322 Converting downloaded kernel to a uImage
201 12:39:29.666622 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/kernel/Image /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/kernel/uImage
202 12:39:30.117021 output: Image Name:
203 12:39:30.117427 output: Created: Mon Nov 4 12:39:29 2024
204 12:39:30.117636 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 12:39:30.117839 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 12:39:30.118037 output: Load Address: 01080000
207 12:39:30.118235 output: Entry Point: 01080000
208 12:39:30.118432 output:
209 12:39:30.118759 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 12:39:30.119022 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 12:39:30.119290 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 12:39:30.119542 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 12:39:30.119799 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 12:39:30.120091 Building ramdisk /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk
215 12:39:36.704334 >> 502368 blocks
216 12:39:57.388454 Adding RAMdisk u-boot header.
217 12:39:57.388907 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk.cpio.gz.uboot
218 12:39:58.077371 output: Image Name:
219 12:39:58.077783 output: Created: Mon Nov 4 12:39:57 2024
220 12:39:58.077991 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 12:39:58.078195 output: Data Size: 65713167 Bytes = 64173.01 KiB = 62.67 MiB
222 12:39:58.078394 output: Load Address: 00000000
223 12:39:58.078591 output: Entry Point: 00000000
224 12:39:58.078786 output:
225 12:39:58.079400 rename /var/lib/lava/dispatcher/tmp/933942/extract-overlay-ramdisk-2bzufbge/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot
226 12:39:58.079811 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 12:39:58.080255 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 12:39:58.080841 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 12:39:58.081331 No LXC device requested
230 12:39:58.081870 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 12:39:58.082423 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 12:39:58.082955 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 12:39:58.083403 Checking files for TFTP limit of 4294967296 bytes.
234 12:39:58.086304 end: 1 tftp-deploy (duration 00:00:40) [common]
235 12:39:58.086926 start: 2 uboot-action (timeout 00:05:00) [common]
236 12:39:58.087494 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 12:39:58.088063 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 12:39:58.088618 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 12:39:58.089192 Using kernel file from prepare-kernel: 933942/tftp-deploy-a5u884uo/kernel/uImage
240 12:39:58.089874 substitutions:
241 12:39:58.090325 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 12:39:58.090766 - {DTB_ADDR}: 0x01070000
243 12:39:58.091202 - {DTB}: 933942/tftp-deploy-a5u884uo/dtb/meson-g12b-a311d-libretech-cc.dtb
244 12:39:58.091642 - {INITRD}: 933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot
245 12:39:58.092108 - {KERNEL_ADDR}: 0x01080000
246 12:39:58.092542 - {KERNEL}: 933942/tftp-deploy-a5u884uo/kernel/uImage
247 12:39:58.092977 - {LAVA_MAC}: None
248 12:39:58.093447 - {PRESEED_CONFIG}: None
249 12:39:58.093880 - {PRESEED_LOCAL}: None
250 12:39:58.094310 - {RAMDISK_ADDR}: 0x08000000
251 12:39:58.094737 - {RAMDISK}: 933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot
252 12:39:58.095170 - {ROOT_PART}: None
253 12:39:58.095596 - {ROOT}: None
254 12:39:58.096056 - {SERVER_IP}: 192.168.6.2
255 12:39:58.096492 - {TEE_ADDR}: 0x83000000
256 12:39:58.096919 - {TEE}: None
257 12:39:58.097346 Parsed boot commands:
258 12:39:58.097763 - setenv autoload no
259 12:39:58.098189 - setenv initrd_high 0xffffffff
260 12:39:58.098615 - setenv fdt_high 0xffffffff
261 12:39:58.099035 - dhcp
262 12:39:58.099461 - setenv serverip 192.168.6.2
263 12:39:58.099884 - tftpboot 0x01080000 933942/tftp-deploy-a5u884uo/kernel/uImage
264 12:39:58.100341 - tftpboot 0x08000000 933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot
265 12:39:58.100775 - tftpboot 0x01070000 933942/tftp-deploy-a5u884uo/dtb/meson-g12b-a311d-libretech-cc.dtb
266 12:39:58.101204 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 12:39:58.101636 - bootm 0x01080000 0x08000000 0x01070000
268 12:39:58.102175 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 12:39:58.103787 start: 2.3 connect-device (timeout 00:05:00) [common]
271 12:39:58.104295 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 12:39:58.119672 Setting prompt string to ['lava-test: # ']
273 12:39:58.121285 end: 2.3 connect-device (duration 00:00:00) [common]
274 12:39:58.121935 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 12:39:58.122518 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 12:39:58.123072 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 12:39:58.124358 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 12:39:58.182997 >> OK - accepted request
279 12:39:58.185163 Returned 0 in 0 seconds
280 12:39:58.286323 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 12:39:58.288023 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 12:39:58.288650 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 12:39:58.289199 Setting prompt string to ['Hit any key to stop autoboot']
285 12:39:58.289695 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 12:39:58.291380 Trying 192.168.56.21...
287 12:39:58.291886 Connected to conserv1.
288 12:39:58.292364 Escape character is '^]'.
289 12:39:58.292805
290 12:39:58.293265 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 12:39:58.293735
292 12:40:09.822045 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 12:40:09.822701 bl2_stage_init 0x01
294 12:40:09.823203 bl2_stage_init 0x81
295 12:40:09.827866 hw id: 0x0000 - pwm id 0x01
296 12:40:09.828471 bl2_stage_init 0xc1
297 12:40:09.828933 bl2_stage_init 0x02
298 12:40:09.829380
299 12:40:09.833274 L0:00000000
300 12:40:09.833804 L1:20000703
301 12:40:09.834247 L2:00008067
302 12:40:09.834676 L3:14000000
303 12:40:09.838829 B2:00402000
304 12:40:09.839286 B1:e0f83180
305 12:40:09.839717
306 12:40:09.840183 TE: 58124
307 12:40:09.840614
308 12:40:09.844513 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 12:40:09.844969
310 12:40:09.845398 Board ID = 1
311 12:40:09.849984 Set A53 clk to 24M
312 12:40:09.850432 Set A73 clk to 24M
313 12:40:09.850860 Set clk81 to 24M
314 12:40:09.855620 A53 clk: 1200 MHz
315 12:40:09.856093 A73 clk: 1200 MHz
316 12:40:09.856520 CLK81: 166.6M
317 12:40:09.856939 smccc: 00012a92
318 12:40:09.861260 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 12:40:09.866825 board id: 1
320 12:40:09.872730 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 12:40:09.883375 fw parse done
322 12:40:09.888563 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 12:40:09.931880 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 12:40:09.942737 PIEI prepare done
325 12:40:09.943200 fastboot data load
326 12:40:09.943637 fastboot data verify
327 12:40:09.948514 verify result: 266
328 12:40:09.954013 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 12:40:09.954509 LPDDR4 probe
330 12:40:09.954961 ddr clk to 1584MHz
331 12:40:09.961996 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 12:40:09.999228
333 12:40:09.999710 dmc_version 0001
334 12:40:10.004953 Check phy result
335 12:40:10.011783 INFO : End of CA training
336 12:40:10.012284 INFO : End of initialization
337 12:40:10.017475 INFO : Training has run successfully!
338 12:40:10.017942 Check phy result
339 12:40:10.022985 INFO : End of initialization
340 12:40:10.023449 INFO : End of read enable training
341 12:40:10.028589 INFO : End of fine write leveling
342 12:40:10.034241 INFO : End of Write leveling coarse delay
343 12:40:10.034704 INFO : Training has run successfully!
344 12:40:10.035153 Check phy result
345 12:40:10.039759 INFO : End of initialization
346 12:40:10.040276 INFO : End of read dq deskew training
347 12:40:10.045475 INFO : End of MPR read delay center optimization
348 12:40:10.050988 INFO : End of write delay center optimization
349 12:40:10.056586 INFO : End of read delay center optimization
350 12:40:10.057068 INFO : End of max read latency training
351 12:40:10.062226 INFO : Training has run successfully!
352 12:40:10.062689 1D training succeed
353 12:40:10.070420 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 12:40:10.118927 Check phy result
355 12:40:10.119395 INFO : End of initialization
356 12:40:10.140664 INFO : End of 2D read delay Voltage center optimization
357 12:40:10.160918 INFO : End of 2D read delay Voltage center optimization
358 12:40:10.213000 INFO : End of 2D write delay Voltage center optimization
359 12:40:10.262336 INFO : End of 2D write delay Voltage center optimization
360 12:40:10.267919 INFO : Training has run successfully!
361 12:40:10.268436
362 12:40:10.268890 channel==0
363 12:40:10.273513 RxClkDly_Margin_A0==88 ps 9
364 12:40:10.273978 TxDqDly_Margin_A0==98 ps 10
365 12:40:10.279098 RxClkDly_Margin_A1==88 ps 9
366 12:40:10.279558 TxDqDly_Margin_A1==88 ps 9
367 12:40:10.280037 TrainedVREFDQ_A0==74
368 12:40:10.284700 TrainedVREFDQ_A1==75
369 12:40:10.285171 VrefDac_Margin_A0==24
370 12:40:10.285609 DeviceVref_Margin_A0==40
371 12:40:10.290325 VrefDac_Margin_A1==25
372 12:40:10.290787 DeviceVref_Margin_A1==39
373 12:40:10.291227
374 12:40:10.291665
375 12:40:10.292141 channel==1
376 12:40:10.296022 RxClkDly_Margin_A0==88 ps 9
377 12:40:10.296491 TxDqDly_Margin_A0==98 ps 10
378 12:40:10.301564 RxClkDly_Margin_A1==98 ps 10
379 12:40:10.302033 TxDqDly_Margin_A1==88 ps 9
380 12:40:10.307108 TrainedVREFDQ_A0==77
381 12:40:10.307572 TrainedVREFDQ_A1==77
382 12:40:10.308047 VrefDac_Margin_A0==22
383 12:40:10.312710 DeviceVref_Margin_A0==37
384 12:40:10.313172 VrefDac_Margin_A1==24
385 12:40:10.318311 DeviceVref_Margin_A1==37
386 12:40:10.318770
387 12:40:10.319213 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 12:40:10.319653
389 12:40:10.351918 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 12:40:10.352518 2D training succeed
391 12:40:10.357535 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 12:40:10.363137 auto size-- 65535DDR cs0 size: 2048MB
393 12:40:10.363609 DDR cs1 size: 2048MB
394 12:40:10.368707 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 12:40:10.369181 cs0 DataBus test pass
396 12:40:10.374320 cs1 DataBus test pass
397 12:40:10.374792 cs0 AddrBus test pass
398 12:40:10.375237 cs1 AddrBus test pass
399 12:40:10.375678
400 12:40:10.379902 100bdlr_step_size ps== 420
401 12:40:10.380410 result report
402 12:40:10.385547 boot times 0Enable ddr reg access
403 12:40:10.390798 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 12:40:10.404252 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 12:40:10.977330 0.0;M3 CHK:0;cm4_sp_mode 0
406 12:40:10.977951 MVN_1=0x00000000
407 12:40:10.982789 MVN_2=0x00000000
408 12:40:10.988560 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 12:40:10.989033 OPS=0x10
410 12:40:10.989482 ring efuse init
411 12:40:10.989924 chipver efuse init
412 12:40:10.994141 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 12:40:10.999747 [0.018961 Inits done]
414 12:40:11.000263 secure task start!
415 12:40:11.000711 high task start!
416 12:40:11.003713 low task start!
417 12:40:11.004216 run into bl31
418 12:40:11.010978 NOTICE: BL31: v1.3(release):4fc40b1
419 12:40:11.018770 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 12:40:11.019247 NOTICE: BL31: G12A normal boot!
421 12:40:11.044108 NOTICE: BL31: BL33 decompress pass
422 12:40:11.049782 ERROR: Error initializing runtime service opteed_fast
423 12:40:12.282598
424 12:40:12.283165
425 12:40:12.291014 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 12:40:12.291484
427 12:40:12.291928 Model: Libre Computer AML-A311D-CC Alta
428 12:40:12.498488 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 12:40:12.522864 DRAM: 2 GiB (effective 3.8 GiB)
430 12:40:12.665847 Core: 408 devices, 31 uclasses, devicetree: separate
431 12:40:12.671664 WDT: Not starting watchdog@f0d0
432 12:40:12.703923 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 12:40:12.716374 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 12:40:12.721352 ** Bad device specification mmc 0 **
435 12:40:12.731794 Card did not respond to voltage select! : -110
436 12:40:12.738381 ** Bad device specification mmc 0 **
437 12:40:12.738845 Couldn't find partition mmc 0
438 12:40:12.747830 Card did not respond to voltage select! : -110
439 12:40:12.753181 ** Bad device specification mmc 0 **
440 12:40:12.753649 Couldn't find partition mmc 0
441 12:40:12.758254 Error: could not access storage.
442 12:40:14.022360 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 12:40:14.022965 bl2_stage_init 0x01
444 12:40:14.023439 bl2_stage_init 0x81
445 12:40:14.027841 hw id: 0x0000 - pwm id 0x01
446 12:40:14.028447 bl2_stage_init 0xc1
447 12:40:14.028910 bl2_stage_init 0x02
448 12:40:14.029360
449 12:40:14.033418 L0:00000000
450 12:40:14.033930 L1:20000703
451 12:40:14.034378 L2:00008067
452 12:40:14.034821 L3:14000000
453 12:40:14.039029 B2:00402000
454 12:40:14.039575 B1:e0f83180
455 12:40:14.040061
456 12:40:14.040515 TE: 58124
457 12:40:14.040958
458 12:40:14.044626 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 12:40:14.045134
460 12:40:14.045590 Board ID = 1
461 12:40:14.050210 Set A53 clk to 24M
462 12:40:14.050715 Set A73 clk to 24M
463 12:40:14.051163 Set clk81 to 24M
464 12:40:14.055820 A53 clk: 1200 MHz
465 12:40:14.056340 A73 clk: 1200 MHz
466 12:40:14.056792 CLK81: 166.6M
467 12:40:14.057237 smccc: 00012a92
468 12:40:14.061411 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 12:40:14.067012 board id: 1
470 12:40:14.071888 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 12:40:14.083580 fw parse done
472 12:40:14.088649 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 12:40:14.132171 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 12:40:14.143126 PIEI prepare done
475 12:40:14.143636 fastboot data load
476 12:40:14.144137 fastboot data verify
477 12:40:14.148666 verify result: 266
478 12:40:14.154254 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 12:40:14.154761 LPDDR4 probe
480 12:40:14.155216 ddr clk to 1584MHz
481 12:40:14.162232 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 12:40:14.198598
483 12:40:14.199108 dmc_version 0001
484 12:40:14.205727 Check phy result
485 12:40:14.212087 INFO : End of CA training
486 12:40:14.212606 INFO : End of initialization
487 12:40:14.217647 INFO : Training has run successfully!
488 12:40:14.218146 Check phy result
489 12:40:14.223254 INFO : End of initialization
490 12:40:14.223755 INFO : End of read enable training
491 12:40:14.228869 INFO : End of fine write leveling
492 12:40:14.234459 INFO : End of Write leveling coarse delay
493 12:40:14.234958 INFO : Training has run successfully!
494 12:40:14.235410 Check phy result
495 12:40:14.240062 INFO : End of initialization
496 12:40:14.240565 INFO : End of read dq deskew training
497 12:40:14.245672 INFO : End of MPR read delay center optimization
498 12:40:14.251238 INFO : End of write delay center optimization
499 12:40:14.256857 INFO : End of read delay center optimization
500 12:40:14.257364 INFO : End of max read latency training
501 12:40:14.262430 INFO : Training has run successfully!
502 12:40:14.262930 1D training succeed
503 12:40:14.271724 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 12:40:14.318345 Check phy result
505 12:40:14.318864 INFO : End of initialization
506 12:40:14.341869 INFO : End of 2D read delay Voltage center optimization
507 12:40:14.362368 INFO : End of 2D read delay Voltage center optimization
508 12:40:14.414275 INFO : End of 2D write delay Voltage center optimization
509 12:40:14.463493 INFO : End of 2D write delay Voltage center optimization
510 12:40:14.469070 INFO : Training has run successfully!
511 12:40:14.469551
512 12:40:14.470006 channel==0
513 12:40:14.474607 RxClkDly_Margin_A0==88 ps 9
514 12:40:14.475095 TxDqDly_Margin_A0==98 ps 10
515 12:40:14.480170 RxClkDly_Margin_A1==88 ps 9
516 12:40:14.480637 TxDqDly_Margin_A1==88 ps 9
517 12:40:14.481081 TrainedVREFDQ_A0==74
518 12:40:14.485791 TrainedVREFDQ_A1==74
519 12:40:14.486261 VrefDac_Margin_A0==24
520 12:40:14.486699 DeviceVref_Margin_A0==40
521 12:40:14.491327 VrefDac_Margin_A1==25
522 12:40:14.491791 DeviceVref_Margin_A1==40
523 12:40:14.492266
524 12:40:14.492711
525 12:40:14.493146 channel==1
526 12:40:14.497041 RxClkDly_Margin_A0==88 ps 9
527 12:40:14.497516 TxDqDly_Margin_A0==98 ps 10
528 12:40:14.502553 RxClkDly_Margin_A1==88 ps 9
529 12:40:14.503020 TxDqDly_Margin_A1==88 ps 9
530 12:40:14.508164 TrainedVREFDQ_A0==77
531 12:40:14.508631 TrainedVREFDQ_A1==77
532 12:40:14.509075 VrefDac_Margin_A0==22
533 12:40:14.513797 DeviceVref_Margin_A0==37
534 12:40:14.514258 VrefDac_Margin_A1==24
535 12:40:14.519341 DeviceVref_Margin_A1==37
536 12:40:14.519804
537 12:40:14.520286 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 12:40:14.520722
539 12:40:14.553112 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 12:40:14.553622 2D training succeed
541 12:40:14.558600 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 12:40:14.564147 auto size-- 65535DDR cs0 size: 2048MB
543 12:40:14.564613 DDR cs1 size: 2048MB
544 12:40:14.569811 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 12:40:14.570276 cs0 DataBus test pass
546 12:40:14.575342 cs1 DataBus test pass
547 12:40:14.575808 cs0 AddrBus test pass
548 12:40:14.576297 cs1 AddrBus test pass
549 12:40:14.576742
550 12:40:14.581055 100bdlr_step_size ps== 420
551 12:40:14.581534 result report
552 12:40:14.586558 boot times 0Enable ddr reg access
553 12:40:14.591721 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 12:40:14.604305 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 12:40:15.179128 0.0;M3 CHK:0;cm4_sp_mode 0
556 12:40:15.179664 MVN_1=0x00000000
557 12:40:15.184694 MVN_2=0x00000000
558 12:40:15.190346 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 12:40:15.190852 OPS=0x10
560 12:40:15.191316 ring efuse init
561 12:40:15.191774 chipver efuse init
562 12:40:15.198506 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 12:40:15.199030 [0.018961 Inits done]
564 12:40:15.206082 secure task start!
565 12:40:15.206536 high task start!
566 12:40:15.206960 low task start!
567 12:40:15.207383 run into bl31
568 12:40:15.212701 NOTICE: BL31: v1.3(release):4fc40b1
569 12:40:15.220533 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 12:40:15.220989 NOTICE: BL31: G12A normal boot!
571 12:40:15.246092 NOTICE: BL31: BL33 decompress pass
572 12:40:15.251502 ERROR: Error initializing runtime service opteed_fast
573 12:40:16.484760
574 12:40:16.485400
575 12:40:16.493116 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 12:40:16.493618
577 12:40:16.494078 Model: Libre Computer AML-A311D-CC Alta
578 12:40:16.701828 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 12:40:16.724949 DRAM: 2 GiB (effective 3.8 GiB)
580 12:40:16.867886 Core: 408 devices, 31 uclasses, devicetree: separate
581 12:40:16.873685 WDT: Not starting watchdog@f0d0
582 12:40:16.905964 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 12:40:16.918338 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 12:40:16.923381 ** Bad device specification mmc 0 **
585 12:40:16.933636 Card did not respond to voltage select! : -110
586 12:40:16.941406 ** Bad device specification mmc 0 **
587 12:40:16.941893 Couldn't find partition mmc 0
588 12:40:16.949651 Card did not respond to voltage select! : -110
589 12:40:16.955100 ** Bad device specification mmc 0 **
590 12:40:16.955581 Couldn't find partition mmc 0
591 12:40:16.960282 Error: could not access storage.
592 12:40:17.302854 Net: eth0: ethernet@ff3f0000
593 12:40:17.303460 starting USB...
594 12:40:17.555089 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 12:40:17.555651 Starting the controller
596 12:40:17.561521 USB XHCI 1.10
597 12:40:19.274369 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 12:40:19.275054 bl2_stage_init 0x01
599 12:40:19.275526 bl2_stage_init 0x81
600 12:40:19.280019 hw id: 0x0000 - pwm id 0x01
601 12:40:19.280524 bl2_stage_init 0xc1
602 12:40:19.280982 bl2_stage_init 0x02
603 12:40:19.281432
604 12:40:19.285610 L0:00000000
605 12:40:19.286098 L1:20000703
606 12:40:19.286553 L2:00008067
607 12:40:19.286995 L3:14000000
608 12:40:19.291099 B2:00402000
609 12:40:19.291582 B1:e0f83180
610 12:40:19.292061
611 12:40:19.292512 TE: 58124
612 12:40:19.292960
613 12:40:19.296797 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 12:40:19.297292
615 12:40:19.297739 Board ID = 1
616 12:40:19.302358 Set A53 clk to 24M
617 12:40:19.302839 Set A73 clk to 24M
618 12:40:19.303286 Set clk81 to 24M
619 12:40:19.308008 A53 clk: 1200 MHz
620 12:40:19.308499 A73 clk: 1200 MHz
621 12:40:19.308951 CLK81: 166.6M
622 12:40:19.309392 smccc: 00012a92
623 12:40:19.313541 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 12:40:19.319131 board id: 1
625 12:40:19.325086 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 12:40:19.335658 fw parse done
627 12:40:19.341509 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 12:40:19.384193 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 12:40:19.395050 PIEI prepare done
630 12:40:19.395558 fastboot data load
631 12:40:19.396053 fastboot data verify
632 12:40:19.400646 verify result: 266
633 12:40:19.406228 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 12:40:19.406709 LPDDR4 probe
635 12:40:19.407155 ddr clk to 1584MHz
636 12:40:19.414204 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 12:40:19.451565
638 12:40:19.452204 dmc_version 0001
639 12:40:19.458167 Check phy result
640 12:40:19.464075 INFO : End of CA training
641 12:40:19.464568 INFO : End of initialization
642 12:40:19.469692 INFO : Training has run successfully!
643 12:40:19.470177 Check phy result
644 12:40:19.475220 INFO : End of initialization
645 12:40:19.475698 INFO : End of read enable training
646 12:40:19.478540 INFO : End of fine write leveling
647 12:40:19.484181 INFO : End of Write leveling coarse delay
648 12:40:19.489760 INFO : Training has run successfully!
649 12:40:19.490245 Check phy result
650 12:40:19.490690 INFO : End of initialization
651 12:40:19.495352 INFO : End of read dq deskew training
652 12:40:19.500954 INFO : End of MPR read delay center optimization
653 12:40:19.501437 INFO : End of write delay center optimization
654 12:40:19.506542 INFO : End of read delay center optimization
655 12:40:19.512225 INFO : End of max read latency training
656 12:40:19.512705 INFO : Training has run successfully!
657 12:40:19.517762 1D training succeed
658 12:40:19.523634 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 12:40:19.571271 Check phy result
660 12:40:19.571797 INFO : End of initialization
661 12:40:19.592956 INFO : End of 2D read delay Voltage center optimization
662 12:40:19.613216 INFO : End of 2D read delay Voltage center optimization
663 12:40:19.665238 INFO : End of 2D write delay Voltage center optimization
664 12:40:19.714612 INFO : End of 2D write delay Voltage center optimization
665 12:40:19.720223 INFO : Training has run successfully!
666 12:40:19.720703
667 12:40:19.721152 channel==0
668 12:40:19.725789 RxClkDly_Margin_A0==88 ps 9
669 12:40:19.726267 TxDqDly_Margin_A0==108 ps 11
670 12:40:19.731401 RxClkDly_Margin_A1==88 ps 9
671 12:40:19.731893 TxDqDly_Margin_A1==98 ps 10
672 12:40:19.732593 TrainedVREFDQ_A0==74
673 12:40:19.737001 TrainedVREFDQ_A1==74
674 12:40:19.737476 VrefDac_Margin_A0==25
675 12:40:19.742576 DeviceVref_Margin_A0==40
676 12:40:19.743031 VrefDac_Margin_A1==25
677 12:40:19.743447 DeviceVref_Margin_A1==40
678 12:40:19.743854
679 12:40:19.744298
680 12:40:19.748202 channel==1
681 12:40:19.748656 RxClkDly_Margin_A0==88 ps 9
682 12:40:19.749074 TxDqDly_Margin_A0==98 ps 10
683 12:40:19.753796 RxClkDly_Margin_A1==98 ps 10
684 12:40:19.754248 TxDqDly_Margin_A1==88 ps 9
685 12:40:19.759397 TrainedVREFDQ_A0==77
686 12:40:19.759854 TrainedVREFDQ_A1==77
687 12:40:19.760315 VrefDac_Margin_A0==22
688 12:40:19.764975 DeviceVref_Margin_A0==37
689 12:40:19.765436 VrefDac_Margin_A1==22
690 12:40:19.770589 DeviceVref_Margin_A1==37
691 12:40:19.771046
692 12:40:19.771460 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 12:40:19.776204
694 12:40:19.804419 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 12:40:19.805000 2D training succeed
696 12:40:19.809901 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 12:40:19.815482 auto size-- 65535DDR cs0 size: 2048MB
698 12:40:19.816023 DDR cs1 size: 2048MB
699 12:40:19.821084 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 12:40:19.821590 cs0 DataBus test pass
701 12:40:19.826708 cs1 DataBus test pass
702 12:40:19.827216 cs0 AddrBus test pass
703 12:40:19.827634 cs1 AddrBus test pass
704 12:40:19.828081
705 12:40:19.832312 100bdlr_step_size ps== 420
706 12:40:19.832843 result report
707 12:40:19.837880 boot times 0Enable ddr reg access
708 12:40:19.843337 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 12:40:19.856877 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 12:40:20.430383 0.0;M3 CHK:0;cm4_sp_mode 0
711 12:40:20.431023 MVN_1=0x00000000
712 12:40:20.436193 MVN_2=0x00000000
713 12:40:20.441688 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 12:40:20.442379 OPS=0x10
715 12:40:20.442905 ring efuse init
716 12:40:20.443487 chipver efuse init
717 12:40:20.447187 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 12:40:20.453055 [0.018961 Inits done]
719 12:40:20.453759 secure task start!
720 12:40:20.454280 high task start!
721 12:40:20.457375 low task start!
722 12:40:20.458038 run into bl31
723 12:40:20.464145 NOTICE: BL31: v1.3(release):4fc40b1
724 12:40:20.471880 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 12:40:20.472483 NOTICE: BL31: G12A normal boot!
726 12:40:20.497205 NOTICE: BL31: BL33 decompress pass
727 12:40:20.502929 ERROR: Error initializing runtime service opteed_fast
728 12:40:21.735954
729 12:40:21.736671
730 12:40:21.744404 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 12:40:21.744968
732 12:40:21.745436 Model: Libre Computer AML-A311D-CC Alta
733 12:40:21.952631 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 12:40:21.976363 DRAM: 2 GiB (effective 3.8 GiB)
735 12:40:22.119233 Core: 408 devices, 31 uclasses, devicetree: separate
736 12:40:22.124937 WDT: Not starting watchdog@f0d0
737 12:40:22.157189 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 12:40:22.169614 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 12:40:22.174616 ** Bad device specification mmc 0 **
740 12:40:22.184965 Card did not respond to voltage select! : -110
741 12:40:22.192602 ** Bad device specification mmc 0 **
742 12:40:22.193144 Couldn't find partition mmc 0
743 12:40:22.200990 Card did not respond to voltage select! : -110
744 12:40:22.206451 ** Bad device specification mmc 0 **
745 12:40:22.206988 Couldn't find partition mmc 0
746 12:40:22.211534 Error: could not access storage.
747 12:40:22.553962 Net: eth0: ethernet@ff3f0000
748 12:40:22.554596 starting USB...
749 12:40:22.805806 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 12:40:22.806390 Starting the controller
751 12:40:22.812781 USB XHCI 1.10
752 12:40:24.972973 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 12:40:24.973645 bl2_stage_init 0x01
754 12:40:24.974119 bl2_stage_init 0x81
755 12:40:24.978788 hw id: 0x0000 - pwm id 0x01
756 12:40:24.979326 bl2_stage_init 0xc1
757 12:40:24.979787 bl2_stage_init 0x02
758 12:40:24.980290
759 12:40:24.984232 L0:00000000
760 12:40:24.984753 L1:20000703
761 12:40:24.985209 L2:00008067
762 12:40:24.985652 L3:14000000
763 12:40:24.987200 B2:00402000
764 12:40:24.987713 B1:e0f83180
765 12:40:24.988208
766 12:40:24.988664 TE: 58167
767 12:40:24.989109
768 12:40:24.998232 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 12:40:24.998773
770 12:40:24.999232 Board ID = 1
771 12:40:24.999679 Set A53 clk to 24M
772 12:40:25.000158 Set A73 clk to 24M
773 12:40:25.003954 Set clk81 to 24M
774 12:40:25.004496 A53 clk: 1200 MHz
775 12:40:25.004950 A73 clk: 1200 MHz
776 12:40:25.007449 CLK81: 166.6M
777 12:40:25.007953 smccc: 00012abd
778 12:40:25.012959 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 12:40:25.018640 board id: 1
780 12:40:25.023833 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 12:40:25.034369 fw parse done
782 12:40:25.040355 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 12:40:25.082827 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 12:40:25.093746 PIEI prepare done
785 12:40:25.094297 fastboot data load
786 12:40:25.094756 fastboot data verify
787 12:40:25.099341 verify result: 266
788 12:40:25.104944 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 12:40:25.105524 LPDDR4 probe
790 12:40:25.105985 ddr clk to 1584MHz
791 12:40:25.112953 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 12:40:25.150244
793 12:40:25.150796 dmc_version 0001
794 12:40:25.156879 Check phy result
795 12:40:25.162745 INFO : End of CA training
796 12:40:25.163256 INFO : End of initialization
797 12:40:25.168365 INFO : Training has run successfully!
798 12:40:25.168886 Check phy result
799 12:40:25.173954 INFO : End of initialization
800 12:40:25.174468 INFO : End of read enable training
801 12:40:25.179587 INFO : End of fine write leveling
802 12:40:25.185155 INFO : End of Write leveling coarse delay
803 12:40:25.185676 INFO : Training has run successfully!
804 12:40:25.186133 Check phy result
805 12:40:25.190765 INFO : End of initialization
806 12:40:25.191281 INFO : End of read dq deskew training
807 12:40:25.196342 INFO : End of MPR read delay center optimization
808 12:40:25.201956 INFO : End of write delay center optimization
809 12:40:25.207574 INFO : End of read delay center optimization
810 12:40:25.208161 INFO : End of max read latency training
811 12:40:25.213154 INFO : Training has run successfully!
812 12:40:25.213667 1D training succeed
813 12:40:25.222293 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 12:40:25.269924 Check phy result
815 12:40:25.270479 INFO : End of initialization
816 12:40:25.292441 INFO : End of 2D read delay Voltage center optimization
817 12:40:25.312681 INFO : End of 2D read delay Voltage center optimization
818 12:40:25.364792 INFO : End of 2D write delay Voltage center optimization
819 12:40:25.414145 INFO : End of 2D write delay Voltage center optimization
820 12:40:25.419699 INFO : Training has run successfully!
821 12:40:25.420267
822 12:40:25.420730 channel==0
823 12:40:25.425307 RxClkDly_Margin_A0==88 ps 9
824 12:40:25.425824 TxDqDly_Margin_A0==98 ps 10
825 12:40:25.428648 RxClkDly_Margin_A1==88 ps 9
826 12:40:25.429159 TxDqDly_Margin_A1==88 ps 9
827 12:40:25.434211 TrainedVREFDQ_A0==74
828 12:40:25.434738 TrainedVREFDQ_A1==74
829 12:40:25.435208 VrefDac_Margin_A0==25
830 12:40:25.439846 DeviceVref_Margin_A0==40
831 12:40:25.440423 VrefDac_Margin_A1==24
832 12:40:25.445417 DeviceVref_Margin_A1==40
833 12:40:25.445939
834 12:40:25.446375
835 12:40:25.446801 channel==1
836 12:40:25.447226 RxClkDly_Margin_A0==98 ps 10
837 12:40:25.451026 TxDqDly_Margin_A0==88 ps 9
838 12:40:25.451535 RxClkDly_Margin_A1==88 ps 9
839 12:40:25.456621 TxDqDly_Margin_A1==88 ps 9
840 12:40:25.457129 TrainedVREFDQ_A0==77
841 12:40:25.457562 TrainedVREFDQ_A1==77
842 12:40:25.462202 VrefDac_Margin_A0==22
843 12:40:25.462699 DeviceVref_Margin_A0==37
844 12:40:25.467800 VrefDac_Margin_A1==24
845 12:40:25.468330 DeviceVref_Margin_A1==37
846 12:40:25.468761
847 12:40:25.473408 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 12:40:25.473911
849 12:40:25.501369 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000018 00000017 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 12:40:25.507002 2D training succeed
851 12:40:25.512607 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 12:40:25.513111 auto size-- 65535DDR cs0 size: 2048MB
853 12:40:25.518181 DDR cs1 size: 2048MB
854 12:40:25.518687 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 12:40:25.523799 cs0 DataBus test pass
856 12:40:25.524338 cs1 DataBus test pass
857 12:40:25.524771 cs0 AddrBus test pass
858 12:40:25.529406 cs1 AddrBus test pass
859 12:40:25.529907
860 12:40:25.530336 100bdlr_step_size ps== 420
861 12:40:25.530770 result report
862 12:40:25.534975 boot times 0Enable ddr reg access
863 12:40:25.542459 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 12:40:25.555929 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 12:40:26.129722 0.0;M3 CHK:0;cm4_sp_mode 0
866 12:40:26.130365 MVN_1=0x00000000
867 12:40:26.135172 MVN_2=0x00000000
868 12:40:26.140918 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 12:40:26.141442 OPS=0x10
870 12:40:26.141899 ring efuse init
871 12:40:26.142346 chipver efuse init
872 12:40:26.149101 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 12:40:26.149637 [0.018961 Inits done]
874 12:40:26.156782 secure task start!
875 12:40:26.157300 high task start!
876 12:40:26.157756 low task start!
877 12:40:26.158203 run into bl31
878 12:40:26.163377 NOTICE: BL31: v1.3(release):4fc40b1
879 12:40:26.171180 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 12:40:26.171708 NOTICE: BL31: G12A normal boot!
881 12:40:26.196607 NOTICE: BL31: BL33 decompress pass
882 12:40:26.202207 ERROR: Error initializing runtime service opteed_fast
883 12:40:27.435099
884 12:40:27.435765
885 12:40:27.443550 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 12:40:27.444116
887 12:40:27.444672 Model: Libre Computer AML-A311D-CC Alta
888 12:40:27.651856 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 12:40:27.675149 DRAM: 2 GiB (effective 3.8 GiB)
890 12:40:27.818137 Core: 408 devices, 31 uclasses, devicetree: separate
891 12:40:27.824167 WDT: Not starting watchdog@f0d0
892 12:40:27.856261 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 12:40:27.868755 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 12:40:27.873717 ** Bad device specification mmc 0 **
895 12:40:27.884123 Card did not respond to voltage select! : -110
896 12:40:27.891730 ** Bad device specification mmc 0 **
897 12:40:27.892232 Couldn't find partition mmc 0
898 12:40:27.900045 Card did not respond to voltage select! : -110
899 12:40:27.905547 ** Bad device specification mmc 0 **
900 12:40:27.906011 Couldn't find partition mmc 0
901 12:40:27.910604 Error: could not access storage.
902 12:40:28.254141 Net: eth0: ethernet@ff3f0000
903 12:40:28.254704 starting USB...
904 12:40:28.506082 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 12:40:28.506741 Starting the controller
906 12:40:28.513041 USB XHCI 1.10
907 12:40:30.372743 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 12:40:30.373379 bl2_stage_init 0x01
909 12:40:30.373859 bl2_stage_init 0x81
910 12:40:30.378425 hw id: 0x0000 - pwm id 0x01
911 12:40:30.378970 bl2_stage_init 0xc1
912 12:40:30.379441 bl2_stage_init 0x02
913 12:40:30.379895
914 12:40:30.384052 L0:00000000
915 12:40:30.384597 L1:20000703
916 12:40:30.385061 L2:00008067
917 12:40:30.385511 L3:14000000
918 12:40:30.386937 B2:00402000
919 12:40:30.387472 B1:e0f83180
920 12:40:30.387929
921 12:40:30.388427 TE: 58167
922 12:40:30.388885
923 12:40:30.398057 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 12:40:30.398612
925 12:40:30.399075 Board ID = 1
926 12:40:30.399527 Set A53 clk to 24M
927 12:40:30.399973 Set A73 clk to 24M
928 12:40:30.403708 Set clk81 to 24M
929 12:40:30.404279 A53 clk: 1200 MHz
930 12:40:30.404744 A73 clk: 1200 MHz
931 12:40:30.407225 CLK81: 166.6M
932 12:40:30.407757 smccc: 00012abe
933 12:40:30.412629 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 12:40:30.418358 board id: 1
935 12:40:30.423479 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 12:40:30.434161 fw parse done
937 12:40:30.440091 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 12:40:30.482618 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 12:40:30.493597 PIEI prepare done
940 12:40:30.494134 fastboot data load
941 12:40:30.494573 fastboot data verify
942 12:40:30.499225 verify result: 266
943 12:40:30.504808 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 12:40:30.505343 LPDDR4 probe
945 12:40:30.505777 ddr clk to 1584MHz
946 12:40:30.512801 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 12:40:30.550040
948 12:40:30.550588 dmc_version 0001
949 12:40:30.556724 Check phy result
950 12:40:30.562585 INFO : End of CA training
951 12:40:30.563113 INFO : End of initialization
952 12:40:30.568264 INFO : Training has run successfully!
953 12:40:30.568797 Check phy result
954 12:40:30.573796 INFO : End of initialization
955 12:40:30.574352 INFO : End of read enable training
956 12:40:30.577203 INFO : End of fine write leveling
957 12:40:30.582680 INFO : End of Write leveling coarse delay
958 12:40:30.588281 INFO : Training has run successfully!
959 12:40:30.588824 Check phy result
960 12:40:30.589287 INFO : End of initialization
961 12:40:30.593903 INFO : End of read dq deskew training
962 12:40:30.599468 INFO : End of MPR read delay center optimization
963 12:40:30.600042 INFO : End of write delay center optimization
964 12:40:30.605034 INFO : End of read delay center optimization
965 12:40:30.610652 INFO : End of max read latency training
966 12:40:30.611185 INFO : Training has run successfully!
967 12:40:30.616316 1D training succeed
968 12:40:30.622277 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 12:40:30.669823 Check phy result
970 12:40:30.670385 INFO : End of initialization
971 12:40:30.691503 INFO : End of 2D read delay Voltage center optimization
972 12:40:30.711760 INFO : End of 2D read delay Voltage center optimization
973 12:40:30.763862 INFO : End of 2D write delay Voltage center optimization
974 12:40:30.813173 INFO : End of 2D write delay Voltage center optimization
975 12:40:30.818775 INFO : Training has run successfully!
976 12:40:30.819315
977 12:40:30.819785 channel==0
978 12:40:30.824382 RxClkDly_Margin_A0==88 ps 9
979 12:40:30.824918 TxDqDly_Margin_A0==98 ps 10
980 12:40:30.829876 RxClkDly_Margin_A1==88 ps 9
981 12:40:30.830406 TxDqDly_Margin_A1==88 ps 9
982 12:40:30.830875 TrainedVREFDQ_A0==74
983 12:40:30.835527 TrainedVREFDQ_A1==74
984 12:40:30.836102 VrefDac_Margin_A0==25
985 12:40:30.836572 DeviceVref_Margin_A0==40
986 12:40:30.841098 VrefDac_Margin_A1==25
987 12:40:30.841633 DeviceVref_Margin_A1==40
988 12:40:30.842091
989 12:40:30.842541
990 12:40:30.842986 channel==1
991 12:40:30.846862 RxClkDly_Margin_A0==98 ps 10
992 12:40:30.847396 TxDqDly_Margin_A0==98 ps 10
993 12:40:30.852378 RxClkDly_Margin_A1==98 ps 10
994 12:40:30.852914 TxDqDly_Margin_A1==88 ps 9
995 12:40:30.857892 TrainedVREFDQ_A0==77
996 12:40:30.858424 TrainedVREFDQ_A1==77
997 12:40:30.858883 VrefDac_Margin_A0==22
998 12:40:30.863572 DeviceVref_Margin_A0==37
999 12:40:30.864137 VrefDac_Margin_A1==22
1000 12:40:30.869172 DeviceVref_Margin_A1==37
1001 12:40:30.869703
1002 12:40:30.870163 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 12:40:30.870616
1004 12:40:30.902777 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 12:40:30.903393 2D training succeed
1006 12:40:30.908445 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 12:40:30.913841 auto size-- 65535DDR cs0 size: 2048MB
1008 12:40:30.914389 DDR cs1 size: 2048MB
1009 12:40:30.919428 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 12:40:30.919968 cs0 DataBus test pass
1011 12:40:30.925025 cs1 DataBus test pass
1012 12:40:30.925562 cs0 AddrBus test pass
1013 12:40:30.926022 cs1 AddrBus test pass
1014 12:40:30.926468
1015 12:40:30.930634 100bdlr_step_size ps== 420
1016 12:40:30.931182 result report
1017 12:40:30.936293 boot times 0Enable ddr reg access
1018 12:40:30.941589 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 12:40:30.955026 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 12:40:31.528773 0.0;M3 CHK:0;cm4_sp_mode 0
1021 12:40:31.529458 MVN_1=0x00000000
1022 12:40:31.534278 MVN_2=0x00000000
1023 12:40:31.539960 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 12:40:31.540559 OPS=0x10
1025 12:40:31.541031 ring efuse init
1026 12:40:31.541484 chipver efuse init
1027 12:40:31.548308 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 12:40:31.548870 [0.018961 Inits done]
1029 12:40:31.549337 secure task start!
1030 12:40:31.555773 high task start!
1031 12:40:31.556343 low task start!
1032 12:40:31.556813 run into bl31
1033 12:40:31.562392 NOTICE: BL31: v1.3(release):4fc40b1
1034 12:40:31.570193 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 12:40:31.570745 NOTICE: BL31: G12A normal boot!
1036 12:40:31.595577 NOTICE: BL31: BL33 decompress pass
1037 12:40:31.601315 ERROR: Error initializing runtime service opteed_fast
1038 12:40:32.834085
1039 12:40:32.834761
1040 12:40:32.842558 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 12:40:32.843134
1042 12:40:32.843605 Model: Libre Computer AML-A311D-CC Alta
1043 12:40:33.050932 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 12:40:33.074356 DRAM: 2 GiB (effective 3.8 GiB)
1045 12:40:33.217317 Core: 408 devices, 31 uclasses, devicetree: separate
1046 12:40:33.223163 WDT: Not starting watchdog@f0d0
1047 12:40:33.255426 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 12:40:33.267796 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 12:40:33.272857 ** Bad device specification mmc 0 **
1050 12:40:33.283177 Card did not respond to voltage select! : -110
1051 12:40:33.290843 ** Bad device specification mmc 0 **
1052 12:40:33.291382 Couldn't find partition mmc 0
1053 12:40:33.299163 Card did not respond to voltage select! : -110
1054 12:40:33.304685 ** Bad device specification mmc 0 **
1055 12:40:33.305211 Couldn't find partition mmc 0
1056 12:40:33.309770 Error: could not access storage.
1057 12:40:33.652366 Net: eth0: ethernet@ff3f0000
1058 12:40:33.653009 starting USB...
1059 12:40:33.904162 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 12:40:33.904769 Starting the controller
1061 12:40:33.911072 USB XHCI 1.10
1062 12:40:35.467334 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 12:40:35.475651 scanning usb for storage devices... 0 Storage Device(s) found
1065 12:40:35.527386 Hit any key to stop autoboot: 1
1066 12:40:35.528377 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 12:40:35.529037 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 12:40:35.529542 Setting prompt string to ['=>']
1069 12:40:35.530050 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 12:40:35.543005 0
1071 12:40:35.543951 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 12:40:35.544513 Sending with 10 millisecond of delay
1074 12:40:36.679308 => setenv autoload no
1075 12:40:36.690174 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 12:40:36.695566 setenv autoload no
1077 12:40:36.696391 Sending with 10 millisecond of delay
1079 12:40:38.493340 => setenv initrd_high 0xffffffff
1080 12:40:38.504195 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 12:40:38.505144 setenv initrd_high 0xffffffff
1082 12:40:38.505918 Sending with 10 millisecond of delay
1084 12:40:40.122244 => setenv fdt_high 0xffffffff
1085 12:40:40.133088 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 12:40:40.133990 setenv fdt_high 0xffffffff
1087 12:40:40.134768 Sending with 10 millisecond of delay
1089 12:40:40.426660 => dhcp
1090 12:40:40.437394 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 12:40:40.438258 dhcp
1092 12:40:40.438743 Speed: 1000, full duplex
1093 12:40:40.439194 BOOTP broadcast 1
1094 12:40:40.446350 DHCP client bound to address 192.168.6.27 (9 ms)
1095 12:40:40.447121 Sending with 10 millisecond of delay
1097 12:40:42.123693 => setenv serverip 192.168.6.2
1098 12:40:42.137552 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 12:40:42.138583 setenv serverip 192.168.6.2
1100 12:40:42.139333 Sending with 10 millisecond of delay
1102 12:40:45.862804 => tftpboot 0x01080000 933942/tftp-deploy-a5u884uo/kernel/uImage
1103 12:40:45.873646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 12:40:45.874556 tftpboot 0x01080000 933942/tftp-deploy-a5u884uo/kernel/uImage
1105 12:40:45.875045 Speed: 1000, full duplex
1106 12:40:45.875507 Using ethernet@ff3f0000 device
1107 12:40:45.876769 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 12:40:45.882058 Filename '933942/tftp-deploy-a5u884uo/kernel/uImage'.
1109 12:40:45.886070 Load address: 0x1080000
1110 12:40:48.768902 Loading: *################################################## 43.6 MiB
1111 12:40:48.769542 15.1 MiB/s
1112 12:40:48.770019 done
1113 12:40:48.773445 Bytes transferred = 45713984 (2b98a40 hex)
1114 12:40:48.774294 Sending with 10 millisecond of delay
1116 12:40:53.464381 => tftpboot 0x08000000 933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot
1117 12:40:53.475231 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 12:40:53.476161 tftpboot 0x08000000 933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot
1119 12:40:53.476659 Speed: 1000, full duplex
1120 12:40:53.477118 Using ethernet@ff3f0000 device
1121 12:40:53.478082 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 12:40:53.486672 Filename '933942/tftp-deploy-a5u884uo/ramdisk/ramdisk.cpio.gz.uboot'.
1123 12:40:53.487234 Load address: 0x8000000
1124 12:41:02.813907 Loading: *########T ############################# UDP wrong checksum 000000ff 000089fe
1125 12:41:02.864821 # UDP wrong checksum 000000ff 000013f1
1126 12:41:04.033196 ########### UDP wrong checksum 0000000f 000065ae
1127 12:41:09.035127 T UDP wrong checksum 0000000f 000065ae
1128 12:41:19.036959 T T UDP wrong checksum 0000000f 000065ae
1129 12:41:39.041233 T T T T UDP wrong checksum 0000000f 000065ae
1130 12:41:54.045231 T T
1131 12:41:54.045618 Retry count exceeded; starting again
1133 12:41:54.048238 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
1136 12:41:54.050169 end: 2.4 uboot-commands (duration 00:01:56) [common]
1138 12:41:54.051482 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1140 12:41:54.052518 end: 2 uboot-action (duration 00:01:56) [common]
1142 12:41:54.054000 Cleaning after the job
1143 12:41:54.054533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/ramdisk
1144 12:41:54.056875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/kernel
1145 12:41:54.101683 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/dtb
1146 12:41:54.102446 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933942/tftp-deploy-a5u884uo/modules
1147 12:41:54.123875 start: 4.1 power-off (timeout 00:00:30) [common]
1148 12:41:54.124567 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1149 12:41:54.158315 >> OK - accepted request
1150 12:41:54.160684 Returned 0 in 0 seconds
1151 12:41:54.261674 end: 4.1 power-off (duration 00:00:00) [common]
1153 12:41:54.262611 start: 4.2 read-feedback (timeout 00:10:00) [common]
1154 12:41:54.263271 Listened to connection for namespace 'common' for up to 1s
1155 12:41:55.264225 Finalising connection for namespace 'common'
1156 12:41:55.264905 Disconnecting from shell: Finalise
1157 12:41:55.265428 =>
1158 12:41:55.366342 end: 4.2 read-feedback (duration 00:00:01) [common]
1159 12:41:55.366973 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933942
1160 12:41:55.978013 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933942
1161 12:41:55.978628 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.